ASIC Verification

J.Jenithnizanth,

No. ** Nehru street, Udumalpet,

Tirupur district, Tamilnadu-642126,

Mobile: +91-971*******,+91-953*******

Email: **********@*****.***

CAREER OBJECTIVES:

To be a part of the team which is striving for triumph in today’s competitive world where I can make use of my potential for personal growth with the growth of your organization.

ACADEMIC PROFILE:

2008-2012 : B.E. Electronics and Communication Engineering – Karpagam College of Engineering,

Coimbatore- Anna University – 7.12 CGPA

2008 : HSC-R.V.G Higher Secondary School, Kuruchikottai – 76%.

2006 : SSLC– R.V.G Higher Secondary School, Kuruchikottai -81%.

PROFESSIONAL EXPERIENCE:

Total Experience: 6 Months training (ASIC-DESIGN&VERIFICATION)

Certification : ASIC Design and Verification Engineer-Internship Training at SMART CHIP DESIGN Pvt.Ltd Bangalore from APRIL-14 to SEP-14.

Certification : BSNL certified RF Engineer from 2012-June to 2012-July.

SKILLS:

Good knowledge in Digital design.

Experience with RTL (verilog) coding and synthesis.

Good knowledge in Building verification Environment in SystemVerilog and UVM Methodology.

Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog.

Experience in using industry standard EDA tools for the front-end design and verification.

Strong fundamental understanding of RTL simulation and verification methodologies (UVM).

Good knowledge in LTE, CDMA, WCDMA, OFDM Technology.

HDLs : Verilog HDL.

HVL : System Verilog HVL.

Methodologies : UVM.

Language : C, C++, OOPs concepts.

EDA Tools : Questasim.

Domain : ASIC Verification, ASIC Design Flow.

Knowledge : RTL Coding, Simulation, Functional Coverage.

Operating Systems : Linux, XP, windows 7.

Protocols : AMBA AXI, SPI.

Exposure to UNIX : Shell Script.

ASIC PROJECT:

Verification of JK Flip-Flop:

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using system Verilog.

Verified the RTL model using SystemVerilog.

Verification of IP Development for AXI and OCP Interface in UVM:

Knowledge in Architecture and transactions.

Knowledge in Timing diagram and Signal Descriptions.

Develop Interface, transaction, sequencer, monitor, receiver, Scoreboard.

Verification of IP Development SPI Protocol in UVM:

Knowledge in Architecture.

Knowledge in Registers Wishbone Interface signals.

Develop Interface, transaction, sequencer, monitor, receiver, Scoreboard.

Verification of adder in UVM:

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using UVM.

Verified the RTL model using UVM.

B.E PROJECT:

Broadband in MIMO/OFDM

ACHIEVEMENT:

Scored Centum in Mathematics 12th Standard.

PERSONAL DETAILS:

Name : J.Jenithnizanth.

Father’s Name : J.Jacob Thomas.

Mother’s Name : J.Chandra Vathani.

Date Of Birth : 2nd July 1989

Age : 23years

Nationality : Indian

Gender : Male

Marital Status : Single

Langauges Known : English, Tamil

DECLARATION:

I hereby assure you that the information furnished above are true to the best of my knowledge and belief.

Yours faithfully,

JENITHNIZANTH.J

Contact this candidate