Engineer Design

MURALI

Contact No: +91-954-***-****

Email: *********@*****.***

Objective:

2.7 yrs of experience in Digital Design and Verification Engineer. Seeking a Challenging Position in Digital FPGA and ASIC Design, Development, Verification in a State of the Art Technology Leading Company. Open to Relocation and Travel.

Summary:

Strong fundamentals in Digital circuit Design, State Machine Design and VLSI design flow.

Good understanding of the ASIC and FPGA design flow and Digital Design.

Proficient in RTL design, Behavioral simulation and synthesis using Xilinx ISE.

Experience in Serial Communication and Bus Protocols such as UART, SPI, I2C, Router. Knowledge on AMBA Protocol.

Specs to RTL coding, proficient in both Verilog and VHDL. Very efficient in converting specs to RTL, supported by strong background in digital logic design.

Good knowledge in verification on test benches using Verilog HDL

Experienced with Lab Equipments such as Altera FPGA Cyclone-II DES FPGA Board, SPARTAN series and VIRTEX series FPGA Board.

CMOS circuit design and Simulation. Cell level layout design using Magic Layout editor.

Knowledge in CMOS VLSI design.

Result oriented with strong analytical, problem solving, and communication skills.

Self-driven and has the ability to work independently.

Skill Set:

Programming Languages :VerilogHDL, VHDL, Matlab, C, System Verilog (Exposure)

EDA Simulation Tools : Modelsim, Questasim, ISim and XSim

FPGA Design Flow Tool : Xilinx ISE Series, Xilinx Vivado

Layout : MAGIC Layout Editor, Micro wind, DSCH3 Schematic

Bus Architecture Protocols : I2C, SPI, USB2.0, Router, AMBA

Scripting Language : Basics of Perl Scripting

Web Technologies : HTML

Operating Systems : Windows family, Linux

Work Experience:

Currently associated with Nano Scientific Research Centre Pvt. Ltd., Hyderabad as Design & Verification Engineer since Dec 2012.

Worked as VLSI R&D Engineer with St. Mary’s Integrated Campus, Hyderabad from June 2010 to Nov 2012.

Worked as S/W Testing Engineer with Electronics Arts Inc from May 2004 to July 2007

Educational Qualifications:

M.Tech. Microelectronics and VLSI Design. from IIT Madras, Chennai.

B.Tech (ECE) from Nagarjuna University, Guntur, Andhra Pradesh.

Project Profile

Project #1:

Project : Xilinx XSim Simulation

Client : Xilinx

Role : Verification

EDA Tool : Xilinx Vivado, Questasim

Language Used : Verilog and TCL

Description

Xilinx Xsim is an EDA Simulation Tool it supports Verilog, VHDL, System Verilog and Mixed Design Construct.

Myrole

Involved in Xilinx tool GUI testing

Developed Verilog Test cases for simulation.

Involved in RTL simulations, regressed all test cases and created regression status reports.

Debugged the errors and failures at all stages of verification

Project #2:

Project : I2C Protocol

Client : InHouse

Role : Designing and Verification

Description

This project is to design a I2C protocol with single master and three slaves RTC, two EPROM of 2kbytes block should be communicated with processor communication

Myrole

Complete Design is developed in Verilog

Developing the Control sub module and test bench modules.

Coding, Unit Testing and Code reviews.

EDA tool used is Xilinx ISE 12.2i

Conducting debugging with chipscope pro with FPGA implementation.

Delivery documents, Change management, implementation support.

Project #3:

Project : Serial Peripheral Interface (SPI)

Client : InHouse

Role : Design and Verification

Description:

SPI is a synchronous protocol that allows a master device to initiate Communication with

exchanged between these devices. It allows communication between two or more devices at a high

Speed.

Myrole:

Complete Design is developed in Verilog

Architectural design,

Test bench writing.

Project #4:

Project : 1X4 port network Switch verification

Client : InHouse

Role : Design and Verification

Description

This project is design and verification of a 4port switch for network routing between different co-processors application.

Myrole

Developed arbiter module, memory module, in verilog

verification is done using Verilog

simulator used is Questasim

Project #5:

Project : First come First Serve Arbiter

Client : InHouse

Role : Design and Verification

Description

DW_arb_fcfs implements a parameterized, synchronous arbiter based on first-come-first-served priority scheme. In this scheme, on a cycle basis, the client that has been waiting the longest to be issued the grant has the highest priority and the client has just been granted has the lowest priority. This Project implemented and Tested in Xilinx Spartan-3E Basys2 Board.

Myrole

Analysis and design

Worked as a RTL Design, responsible for Coding the product as per specifications

Implemented on FPGA Spartan3E.

Scholastic Achievements:

Scored 99.98 percentile in GATE 2007 (All India 18th Rank).

Qualified Faculty Eligibility Test (FET-2010) conducted by JNTU Hyderabad.

Published and Presented 13 papers at National/International Conferences and International Journals.

Major Strengths

Strong determination to succeed

Highly organized - can priorities work schedules, manage time effectively and meet deadlines

Resourceful, proactive and have initiative

Effective communicator - Can communicate ideas with a wide range of people

Quick learner and hardworking.

Contact this candidate