Project Design
Resume:
RESUME
(Developing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM)
P.RAJKUMAR
Address:
DOOR.NO:-4-63/38
SRI SHIVA SAI COLONY,
NEAR BALAJI HOSPITAL,
N.H.-65, SANGAREDDY,
MEDAK DIST,
TELANGANA STATE.
PIN:-502285
E-mail: *.*************@*****.***
Contact No: +91-854*******
Date of Birth: 18-Nov-1992
CAREER OBJECTIVE:
Aspire to work in an organization which may lead to individual overall growth and complete satisfaction of job along with the growth of the concern organization.
EDUCATIONAL QUALIFICATIONS:
S.No
Degree
Stream
School/
College
Board/
University
Year of Study
Aggregate 1.
B.Tech
ECE
Sri Sai Jyothi Engineering College,
Hyderabad
JNTUH
2010-2014
73.65
2.
Intermediate
MPC
Narayana Junior College,
Chandanagar
Board of Intermediate Education
2008-2010
85.90
3.
SSC
St.Francis High School,Zaheerabad
Board of
Secondary Education
2007-2008
73.40
SUMMARY OF QUALIFICATIONS:
Good understanding of the ASIC and FPGA design flow.
Extensive experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM.
Very good knowledge in verification methodologies.
Experience in using industry standard EDA tools for the front-end design and verification.
TB Methodology: UVM
Protocols: UART, SPI
EDA Tool: Questasim and ISE
PROFESSIONAL SKILLS:
Technical Skills
Universal Verification Methodology(UVM)
System Verilog(SV)
Advanced Verilog
Verilog(EDA tool-Xilinx, Questasim)
Digital Design
Software Skills
C
PROJECT DESCRIPTION:
PROJECT-1: SPI Controller Core - Verification
Institute/Company: MAVEN-SILICON SOFTTECH Pvt. Ltd., Bengalure-76.
Year:2015
HVL : System Verilog
TB Methodology: UVM
EDA Tools: Questasim
Description:
The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.
Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off
PROJECT-2: UART- IP Core – Verification
Institute/Company: MAVEN-SILICON SOFTTECH Pvt. Ltd., Bengalure-76.
Year:2015
HVL : System Verilog
TB Methodology: UVM
EDA Tools: Questasim
Description:
The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in three different modes – Simplex mode, Full Duplex mode and loopback mode.
Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off
PROJECT-3: DESIGN AND SIMULATION OF 1x3 ROUTER
Institute/Company: MAVEN-SILICON SOFTTECH Pvt. Ltd., Bengalure-76.
Year:2015
Description:
It concentrates on developing a serial communication protocol including Master and slave channel to be selected by source as per requested by client. It uses FSM and FIFO concept in order to make communication. There are 3 FIFOs used in router design. It works on the system clock and synchronous active low reset signal and implemented 16x9 memory size of FIFO and test bench developed to verify the design and different test scenarios has tested with different payload data.
Languages used: Verilog-2001 / XILINX-13.2
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL.
Architected the class based verification environment using system Verilog.
Verified the RTL model using SystemVerilog.
Generated functional and code coverage & synthesized the design.
PROJECT-4: DESIGN AND SIMULATION OF WALLACE TREE MULTIPLIER
Institute/Company: Central Institute of Tools Design (CITD), (Central govt.), Balanagar,Hyd-37.
Year:2014
Description:
Power dissipation of integrated circuits is a major concern for VLSI circuit designers. A Wallace tree multiplayer is an improved version of tree based multiplier architecture. It uses a carry save addition algorithm to reduce the latancy. This project aims at further reduction of the latency and power consumption the Wallace tree multiplier. This is made by the use of 4:2, 5:2 compressor and a proposed Wallace tree multiplier is 44.4% faster than the conventional Wallace tree multiplier along with the realization of 11% of reduced power consumption. The simulations have been carried out using the Modelsim and Xilinx tools.
Languages used: Verilog-2001 / Modelsim / Xilinx tools.
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL.
ACTIVITIES AND INTERESTS:
Solving Aptitude & Reasoning related problems.
Swimming, Playing Cricket and Chess.
ACHIEVEMENTS:
Awarded departmental(POLICE-Dept) merit scholarship on account of securing good score in 12th and in B.Tech.
DECLARATION:
I do hereby declare that the above information is true to the best of my knowledge.
Date:
Place: P .RAJKUMAR
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