Project System

MOHAMED SHAHID S Mobile Number: 984-***-****

M.Tech in VLSI Design and Embedded System Email:**************@*****.*** To be a part of a challenging and growing organization, achieve a good reputation of being an honest and hard worker and also to take part in upbringing the company to higher standards. PROFESSIONAL COURSE

As a Project Trainee in M.S. Ramaiah school of Advanced studies, Bangalore (Sep 2013 to may 2014).

TECHNICAL PROFICIENCY

9 months Worked in VLSI & Embedded System Projects on FPGA & ASIC Platform..

Strong knowledge on Coding in Verilog.

Worked on CADENCE with ASIC platforms.

Knowledge on Microcontrollers & operating systems. EDUCATIONAL QUALIFICATION:

M-tech in VLSI &Embedded System from EPCET, Bangalore under Vishwehswariah Technological University.[2012-2014].

Aggregate : 65.04%

BE (Electronics & Communication Egg) (2007-2011) from CIT, Tumkur under Vishwehswariah Technological University.

Aggregate : 55.00%

Pre-University: Sarvodaya PU College, Tumkur (2005-2007) Aggregate : 49.00%

SSLC : Chethana Vidya Mandira, Tumkur (2005)

Aggregate : 72.00%

Technical Knowledge:

Programming Skills : C, Verilog, Assembly language, RTOS Assembly level languages : 8086 microprocessor, 8051 microcontroller, msp430 OBJECTIVE

PROJECTS

M.Tech Final Year Project

Title: ASIC Implementation of Secure Image coding based on DWT and AES Processor Description: In this a new modified version of AES with DWT, to design a compressed and secure image encryption technique, has been implemented. The color image is converted into gray scale image and is compressed by 1-level using Discrete Wavelet Transform, and then it is encrypted using AES. It uses partial encryption technique based on AES-128 bit. From the encrypted data image coefficients are decrypted using Inverse AES and original image coefficient are recovered using IDWT. The result of this coding algorithm and execution are so impressive that as an efficient standard for secure image coding. Tools used: Modelsim, Cadence RTL Compiler, Mat lab, simulink, Xilinx ISE, Language Used: Verilog HDL.

B.E. Project

Title: Automated Teller Machine (ATM)

Description: The aim of the project is to provide banking facility to the small scale Industries, so people can withdrawal money from their available balance (Salary). i-button that provide unique identity number provided to the Clint and having their authenticated PIN number to open their Account and do the transaction.

AREAS OF FIELD INTEREST:

FPGA, ASIC, Verilog/VHDL, Xilinx, Cadence, RTOS, Embedded Systems PERSONAL DETAILS

Name : Mohamed Shahid S

Father's Name : Obedulla

Date of Birth : 19-11-1988

Gender : Male

Marital Status : Single

Hobbies : Blogging, Reading books and magazines.

Yours Sincerely,

(Mohamed Shahid S)

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