Assistant Project

DEEPTI AGGARWAL

Email:********@**.*** **** Progress St, Apt I

Phone: 540-***-**** Blacksburg, VA - 24060

Objective: Seeking full time software developer position

Education

Master of Science in Electrical Engineering GPA:3.75/4.00

Virginia Polytechnic Institute and State University Aug 2013-May 2015

Courses: Multiprocessor programming, Big Database management system, Digital design, Digital VLSI,Theory of

Algorithms

Bachelor of Technology in Instrumentation Engineering GPA: 8.16/10.0

Institute Of Instrumentation, Haryana, India 2007-2011

Courses: Linear Integrated Circuits, Microcontroller, Artificial Intelligence, Computer Organization.

Skill Set: C, C++, Python, Matlab, PostSQL,Java,Verilog (ModelSim), Intel 8085, Intel 8051 and Assembly

Programming.

Professional Certification: Project Management Certification from IPMA in 2011.

Research Experience

Master of Science Thesis:

Research Assistant, Computational Biology and Bioinformatics, ComputerScience May 2014-Aug 2015

Implemented CLR algorithm in C++ for the gene regulatory network inference (Kernel function).

Implemented different inference measures like mutual information, conditional mutual information in C++.

Research Assistant, VT MEMS Laboratory, Virginia Tech Aug 2013-May 2014

Developed LabVIEW program to characterize impedance sensor and generate real-time plots.

Fabricated BioMEMS sensor for the measuring electrical properties of cell.

Fabricated Resistive Memory Devices.

Academic Projects

Get Relevant Information on Disasters (G.R.I.D) using AWS Sept 2014-Dec2014

Implemented Naïve base Classifier and SVM in python for the initial binary classification.

Map reduce was implemented in java using AWS to expand the urls present in tweets.

Transactionally boosted Data Structures in JAVA Sept 2014-Dec2014

Concurrent data structures of hash maps, stacks, and queues in JAVA were implemented.

Implemented TM-based data structures of hash maps, stacks, and queues in JAVA.

8 bit Asynchronous Arbiter in Cadence Virtuoso Sept 2014-Dec2014

Performed Static timing analysis on the 8 bit arbiter in Cadence.

Designed the layout and circuit diagram in Cadence

Communication between two FPGAs through IR stream March 2014-April2014

IR data stream was implemented in Verilog to setup a communication channel between two FPGAs.

Implemented State Machines and generated test signals on FPGA (Quartus board) using ModelSim simulation.

Wireless operated robotic arm June 2010-Feb 2011

Programmed the 8051 movement control circuit in C.

Wireless communication was implemented using RF transmitter and receiver.

Sept 2014-May2014

Characterization of Resistive Memory Devices (Intel Project)

TDDB and voltage test on the Cu-Pt samples

Designed a mask for the new devices with different materials for a lesser breakdown voltage of 4.5V

Professional Experience

2011–2013

Technical Engineer, Punjlloyd Group Ltd., Gurgaon

IOCL Paradip Project: Designed digital logic for automated systems like DCS and ESD/PLC. Reviewed their

technical specification, schematic drawings, and functional diagrams.

ISPRL Mangalore Project: Developed segments for optical transmission of signals from system to the human

machine interface.

Publications:

“Analyses of single-cell mechanoelectrical properties via microfluidics” V. Srinivasaraghavan, D. Aggarwal, H.

Babahosseini, D. Nakidde, J. Strobl and M. Agah. IEEE sensor conference 2014.

Contact this candidate