vlsi design and verification engineer

Snehal Y Jadhav

****,* ****,*********** **** lane, Mobile:+918*********/

Kolhapur,Maharashtra,India,416008 879-***-****

Email:**********@*****.***

Educational Qualification:

DEGREE SCHOOL/COLL BOARD/UNIVERS YEAR MARKS EGE ITY

B.E. KIT’s College of Shivaji University 2014 60.92

Engineering

H.S.C. Vivekanand Maharashtra Board 2010 82.33

College

S.S.C. Tavanappa Patane Maharashtra Board 2008 93.53

High School

Professional Qualification:

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

(January 2015 – June 2015)

VLSI Domain Skills:

HDL: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification - SVA

TB Methodology: UVM

Protocols: UART(ongoing)

EDA Tool: Questasim and ISE

Domain: ASIC/FPGA front-end Design and Verification

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, Assertion Based Verification- SVA

Project Profile:

Sr.No. PROJECT TITLE PROJECT SYNOPSIS

•

1 Visible Light Non-hazardous wireless communication using white light.

Communication(LIFI) • LED as a transmitter and Photodetector as a receiver.

(Aug,2013 - • Using Arduino kit

May,2014) • C programming is used for the transmitter code and receiver

code

VLSI Projects:

1 Verilog Mini Project: HDL: Verilog

RTL Design and HVL: SystemVerilog

Verification TB Methodology: UVM

EDA Tools: Questasim and ISE

• Router 1X3

Description: The router accepts data packets on a single 8-bit port

and routes them to one of the three output channels, channel0,

channel1 and channel2.

Responsibilities:

• Architected the design

• Implemented RTL using Verilog HDL.

• Architected the class based verification environment using

system Verilog

• Verified the RTL model using SystemVerilog.

• Generated functional and code coverage for the RTL

verification sign-off

• Synthesized the design

2 Industry Standard HVL : System Verilog

project TB Methodology: UVM

• Universal EDA Tools: Questasim

Description: The UART IP core provides serial communication

Asynchronous

capabilities, which allow communication with modem or other

Receiver/

external devices. UART will operate in three different modes –

Transmitter IP Core-

Simplex mode, Full Duplex mode and loopback mode.

Verification

Responsibilities:

• Architected the class based verification environment in

UVM

• Verified the RTL module using System Verilog

• Generated functional and code coverage for the RTL

verification sign-off

OTHER ACTIVITIES:

• Participated in various college level as well as national level technical competitions such as

programming competition,paper presentations.

• Completion of ‘training course ‘at BHARAT SANCHAR NIGAM Ltd,Kolhapur.

• Undergone the workshop on Embeded Systems organized by Squre Robotics.

• Participation in 10th annual ISTE state level student’s convention 2011.

• Worked as a co-ordinator in college activities.

PERSONAL PROFILE:

Date of birth : 27 October 1992

Gender : Female

Marital Status : Single

Languages known : Marathi,English,Hindi

Place: Kolhapur

Snehal Jadhav

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