Design Engineering

SHIXIONG JIANG

** ***** **, *** *, Tonawanda, NY 14150

********@*******.*** Tel: 716-***-****

OBJECTIVE

To secure an engineering internship position during summer break. As a Computer Science Ph.D. student, with the

increasing complexity of design and simulation for my current projects, the knowledge I have learned from Campus

and Online are not methodical and detailed enough. I am looking for an opportunity to improve my skills and

understand knowledge deeply.

EDUCATION

University at Buffalo, The State University of New York

Doctor of Philosophy, Computer Science, Expected Dec 2015 GPA:3.6/4.00

Master of Science, Electrical Engineering, May 2012 GPA:3.6/4.00

University of Electronic Science and Technology of China, China

Bachelor of Science, Applied Physics, June 2007 GPA:3.3/4.00

TECHNICAL SKILLS

Programming Language: C, C++, CUDA, OPENMP, MPI, SSE/AVX, Hadoop MapReduce,

Java, Arduino, Matlab, XHTML, CSS

Scripting Language: Perl, PHP

Database systems: MySQL, SQL Server

Operating systems: Mac OS X, GNU/Unix, Windows System

Development tools: Visual Studio, Eclipse, PhpStorm, Vim

Circuit design Language: SPECTRE, SKILL, Verilog, VHDL

EDA Tools: Cadence Virtuoso, Cadence RTL Compiler, Cadence Encounter RTL-to-GDSII,

Xilinx ISE, PSPICE, Mentor Graphics

COMPUTER SCIENCE ENGINEERING RELATED COURSES

Parallel & Distributed Processing Distributed System Operating System

Computer Vision and Image Processing Algorithms Analysis and Design

Introduction to the Theory of Computation Computer Architecture

ELECTRICAL ENGINEERING RELATED COURSES

Introduction to VLSI Electronics Advanced VLSI Design Low Power VLSI Circuit Design

Analog VLSI Circuit Design Fundamentals of Modern VLSI Devices Analog Circuits

Analog Integrated Circuits Layout

COMPUTER SCIENCE ENGINEERING SELECTED PROJECTS

Prime Number Generator and Parallel Bucket Sorting using OPENMP + MPI, CUDA + MPI and SSE/AVX

Parallel programs by using vector-processing environment (SSE/AVX), shared-memory environment

(OPENMP), distributed-memory environment (MPI) and nVidia GPU (CUDA).

Multi-threaded Web Server (implemented with “C

The web server binds to a given port on the given address and waits for incoming HTTP/1.0 requests and serves

content from the given directory.

The server consists of multi threads which are always ready for executing/serving incoming requests. Queuing

thread read the request from the ready queue and based on the scheduling policy issues the request to one of

the available worker threads. Work thread serves the response back to the client and closes the connection.

The scheduling policy can be set between First Come First Serve (FCFS) and Shortest Job First (SJF).

To avoid race condition, I used mutex variables. Only one thread can access the queue at a time to pop or push

the request.

Virtual Memory Manager (implemented with “C

It takes a sequence of page references as an input, as well as the number of available frames, and then

performs the placement of these pages to the available frames using different page replacement policies.

The replacement policy can be set among FIFO, LFU, LRU-STACK, LRU-CLOCK, and LRU-REF8.

Distributed Event Coordination System (implemented with “C

The system consists of a DEC server which can interact and communicate with multiple DEC clients at the same

time.

There are three different requests coming from clients: Insert request, which enter new event ordering

information to sever using happened-before relation; Query request, which ask the relative ordering between

any two events; Reset request, which reset the global vent ordering graph at the server.

ELECTRICAL ENGINEERING SELECTED PROJECTS

Low Power and High speed SRAM and Register File Design (implemented with “Cadence”)

Propose an ultra-low voltage embedded SRAM design for low-power mobile video applications and a hybrid-cell

register files design technique to achieve high reliability. By using Cadence Virtuoso, I have done a lot of Schematic

&& Layout Designs and Simulations.

Low Power and High Speed Content Addressable Memories (implemented with “Cadence”)

Optimize the Content-addressable memory structure based on existing technique named as paralleled Match-line

and Search-line. Obviously improve the comparing speed without sacrificing too much area and power consumption.

Single chip audio frequency amplifier (implemented with “Cadence”)

Design an audio frequency amplifier to satisfy certain requirements, such as Frequency Response, Gain, Phase

Margin and Average power consumption. Hand Calculation by transferring all the transistors into small signal

model. Optimize the performance of the circuit by comparing with simulation results.

16 BIT RISC (implemented with Xilinx using Verilog && Cadence RTL Compiler, Cadence Encounter RTL-to-GDSII)

Implemented a 16-bit RISC microprocessor based on a simplified version of the MIPS architecture. Like the

MIPS instruction-set architecture, my implement included Memory Access Instructions (MAI - Load and Store),

Data Processing Instructions (DPI – ALU) and Control Flow Instructions (CFI - BEQ, BNQ and JUMP).

Convert Verilog into Layout by using RTL Compiler && Encounter RTL-to-GDSII and run simulation.

PS2 keyboard interface (implemented on “Spartan 3E FPGA Board” using Verilog)

Utilized Verilog language designed a PS2 interface circuit. Through the circuit the keyboard can control the

FPGA board and display message on the monitor via VGA.

PUBLICATIONS

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Ultra-Low Voltage Split-data-aware Embedded SRAM for Mobile Video Applications

Clock-biased Local Bit Line for High Performance Register Files

Hybrid-Cell Register Files Design for Improving NBTI Reliability

Variation-and-Aging Aware Low Power embedded SRAM for Multimedia Applications

WORK EXPERIENCE

May 2014 – Dec 2014

C++ Programmer, RepRap 3D printer lab, Dept. of Mechanical and Aerospace at University at Buffalo

In charge of optimizing 3D printer open source code, rebuilding the interface between hardware and software

level according to advanced 3D printer Design by using Arduino with C++ Language. Speed up printing speed

and range obviously.

August 2012 – Present

Teaching Assistant, Dept. of Computer Science at the University at Buffalo. Guide and assist students in their

experiments and labs.

Be responsible for CSE241 Digital Systems (Verilog), CSE590 Computer Architecture (Verilog), CSE593

Introduction to VLSI Electronics (Cadence).

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