M.Tech vlsi design

B.ARTHI ABIRAMI

**/**,******* **** **,

Elur,Namakkal,

Email:***********@*****.***

Mobile:954-***-****

OBJECTIVE:

To attain job which gives me an exposure, knowledge and has to be applied that in

turn gives the profit to the organization.

EDUCATION:

M.Tech(VLSI design) 2015

Karunya University, Coimbatore

CGPA:7.9(upto 3rd semester)

B.E(ECE)

Sasurie College of Engineering- affiliated to Anna University 2012

CGPA:7.1

Class 12

Sri VidhyaMandir Hr. Sec. School- Matriculation 2008

Score:67.3%

Class 10

Sri VidhyaMandir Hr. Sec. School- Matriculation 2006

Score:63.5%

TECHNICAL SKILLS:

Language: Basics in C, C++,VHDL coding

Tools: Xilinx, Tanner EDA, Cadence, Mentor graphics

AREA OF INTEREST:

• Digital Electronics

• CMOS VLSI circuits

• Testing of VLSI circuits

ACHIVEMENTS:

• Presented project in the title “UNIVERSAL SUBSCRIBER IDENDITY

MODULE BASED ATM” in three colleges KATHIR, MPNM,

MAHARAJA PRITHIVI in 2010 Domain : Embedded system

Description: The Transaction has been done by using simcard instead of

using ATM card.

• BE FINAL YEAR PROJECT

Title:Design and implementation of low power full adder using booth

multiplier

Domain: VLSI. Software used: Tanner EDA

Description: Designed a full adder circuit which consumes less power. Then

implemented the proposed full adder in booth multiplier to further consume

less power using tanner EDA tool.

• M.TECH FINAL YEAR PROJECT

PHASE-I

Title: FPGA implementation for frequent pattern text data mining

Domain: Data Mining. Software: Xilinx 14.5

PHASE-II

Title: Memory BIST using low power LFSR as an address generator

Domain: Testing of VLSI circuits. Software: Vivado design suite 2013.3

In plant training:

• Attended In plant training in BSNL, Erode. Where I observed the process of

landline connection and broadband connection.

• Gone for industrial visit in Tessolve, Bangalore.

Workshop:

• Participated in the national level workshop on “VLSI TECHNIQUES” held

on 31st January 2011.

• Participated in the national level workshop on ”VLSI DIGITAL

&ANALOG DESIGN FLOW USING CADENCE TOOL” held on 23 rd and

24th June 2014.

PERSONAL TRAITS:

• Hard worker & Sincere.

• Good in Team Work.

PERSONAL PROFILE:

Father’s Name : R.Balasubramanium

Mother’s Name : B.Mallika

Gender : Female

Date of Birth : 11.06.1991

Languages Known : English, Tamil.

Hobbies : Singing, Drawing.

DECLARATION:

I hereby declare that all the information given here is true to the best of my

knowledge.

Place : Signature

Date : (B.ARTHIABIRAMI)

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