Engineer Engineering

SELVAKUMAR V

E-mail: **********.*****@*****.***

Cell: +91-958*******.

CAREER OBJECTIVE

To apply and expand my engineering skills in the field of VLSI design, with the

opportunity to work on project from conception to completion.

ACADEMIC RECORD

Board of Year of

Qualification Institution Percentage

Examination Passing

Sri Shakthi Institute of

M.E

Anna Engineering and 7.3

(VLSI 2014

University Technology, (CGPA)

DESIGN)

Coimbatore

Er.Perumal

Anna

B.E(ECE) Manimekalai College 66 2010

University

of Engineering, Hosur

Nalanda Matriculation

H.Sc State Board and Hr Sec School, 70 2006

Krishnagiri.

Nalanda Matriculation

S.S.L.C Matriculation and Hr Sec School, 60 2004

Krishnagiri.

SOFTWARE EXPOSURE

HDL Simulators : ModelSim, Xilinx.

FPGA Prototyping : Xilinx FPGA (Chipscope, CoreGen, SystemGen)

Circuit Simulators : Cadence (Virtuoso, rclaunch, and Encounter)

Programming Languages : VHDL, Verilog, System Verilog, C, C++.

Back end : Netlist to gdsii using SOC Encounter

AREA OF INTEREST

Physical Design in VLSI circuits

Logical Designing in VLSI

TECHNICAL SKILLS

Worked on the entire PD Flow from netlist to gdsii (Floorplanning, Power Planning,

Placement & Optimization, CTS, PostCTS optimization,Routing, STA and ECOs for

Timing Fixes )

Good understanding of STA, Timing constraints and Timing fixes.

Good knowledge on Xtalk, EM/IR analysis, antenna, DRC and LVS.

Confident to take complete ownership from netlist to gdsii for blocks.

Effectively completed one blocks from netlist to gdsii.

WORK EXPERIENCE

Company : Adarsha Control & Automation PVT LTD, Bangalore.

Designation : Graduate Trainee Engineer

Job Profile : Work as a Trainee Engineer for the PLC, Automation.

1stApril 2011 to 15thMay 2012

Period :

Company : Sundram Fastners PVT LTD (SFL), Hosur.

Designation : Graduate Engineering Apprentices

Job Profile : Work as a Quality Engineer

11thAugust 2010 to 17th March2011

Period :

WORKSHOPS AND CONFERENCE ATTENDED

Attended the National Level Workshop on “Content Based Image Retrieval & Fusion”

held at Madras Institute of Technology (MIT), Chennai.

Attended the Workshop on “Solid State Device Modeling and Simulation” held at KPR

Institute of Engineering And Technology, Coimbatore.

Presented a paper entitled “AREA OPTIMAZATION OF HIGH SPEED AES FOR

STORAGE AREA NETWORK” in International Conference on (Intelligent

Engineering Systems – 2IES) at EASA College of Engineering and Technology,

Coimbatore.

Presented a paper entitled “Investigation of Hybrid Energy Based Power System Using

Dynamic Load Frequency Control” in National Level Conference (Recent Trends in

Advanced Computing and Communication) at Mahakavi Bharathiyar College of

Engineering And Technology, Tirunelveli.

PROJECTS

Helmet as Wearable Electronics and Safety Ensuring Device using Embedded System.

Area Optimization of High Speed AES for Storage Area Network.

PERSONAL SKILLS

Hard working and ability to complete the work on-time.

Good team worker & motivator.

PERSONAL DETAILS

Father’s Name : Mr. VENKATESAN. V

Gender : Male

Date of Birth : 16-02-1989

Marital Status : Single

Leisure Pursuit : Browsing, Reading and Playing.

Language Proficiency : English(S/R/W), Tamil(S/R/W) and Telugu(S)

Address : 4/25, Kanagamuttlu (Post),

Krishnagiri (Dt),

Tamil Nadu-635002.

DECLARATION

I hereby declare that all the information given here is true to the best of my knowledge and

belief.

Date :

Place :

(SELVAKUMAR V)

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