Design Engineering

AVILOK SHRIVASTAVA

*** ******* ******, **** **** ********@*******.***

California, 94306 917-***-****

OBJECTIVE:

Actively seeking a position in the field of ASIC/FPGA/RTL level/Embedded and PCB design and verification

EDUCATION DETAILS:

Master of Science in Electrical Engineering Feb 2015

University at Buffalo, The State University of New York GPA 3.68/4.0

Bachelor of Technology in Electronics and Communication Engineering May 2012

Jawaharlal Nehru Technological University CGPA 3.95/4.0

TECHNICAL SKILLS:

Languages : C, C++, Embedded C, VHDL, System Verilog, PERL, python

Assembly language : 8051, 8086, ARM, RISC, PIC

Interfaces/Protocols : PCIe, I2C, CAN, SPI, PCI, USB, UART, TCP-IP, RS232/RS485

Tools : Cadence Virtuoso/Spectre, Keil uVision, Xilinx ISE, Aldec HDL, EDA, Synopsys,

CAD, Altium, LabView, SPICE, Matlab, Simulink, OVM, UVM

COURSE WORK:

Intro to VLSI, Advanced VLSI, Microelectronic device fabrication, solid state devices,

Embedded systems, Intro to DSP, Modern VLSI, VHDL and programmable logic design,

Analog circuits and layout, Computer architecture

RELEVANT EXPERIENCE:

Hindustan Aeronautics Limited (H.A.L), India

Hardware Research Intern

• Design specification, RTL description, creating test benches, stating timing analysis, DFT using ATE, place and

route, floor planning, verification and manufacturing of an ASIC that contained RF, digital and analog circuits

• Successfully designed a 16 bit RISC processor using Verilog coding and simulated it on a SPARTAN-6 FPGA

using Xilinx ISE

PROJECT DETAILS:

• Design of a SRAM with power reduction using CADENCE, fall 2013

Succeeded in reducing the power dissipation of SRAM by 14.5% using techniques such as variable threshold voltage and

gated VDD on the cadence platform to implement schematic,layout, timing and power analysis

• Design and simulation of PLL using the CADENCE AMI06 technology, fall 2014

Designed various components of the PLL like Phase frequency detector (PFD), charge pump, low pass filter, VCO and

the divider and validated it on the pad-frame by creating a test bench before fabrication

• 4-bit synchronous counter using VHDL coding of Xilinx’s SPARTAN FPGA, spring 2013

Designed the J-K flip flop, clock divider and a common clock signal on the Atlys board by deriving the inputs to

the flip flops and simulated the behavior on Aldec HDL for waveform generation and simulation

• Brick shooting on ARM CORTEX M3 processor using Embedded C language, spring 2014

Programmed the ARM Cortex M3 processor using Embedded C and designed a user interactive video game with

various game levels built on a NXPLPC1768 board utilizing color,delay and object creation techniques

• Assembly language program for interfacing of DAC with 8086 Microprocessor, spring 2012

Designed an assembly language program for the 8086 microprocessor which used the DAC convertor and generated

waveforms such as sine wave, triangular and square wave

• Interfacing between the Serial Peripheral Interface (SPI) and Peripheral Component Interconnect (PCI)

using System Verilog, fall 2012

Attained an increase in speed of data transfer between the SPI and PCI buses by 19.5% using System Verilog

PROFESSIONAL EXPERIENCE:

AMAZON Development Center, India

• Investigated customers’ online shopping accounts for IP hacking which required precision decision and analytical

precision using tools like Facebook, Google, bank account details and ordering pattern

• Led a team of 20 and achieved an increase in performance of 24.5% executing innovative process techniques

HONOURS AND AWARDS:

Employee Excellence Award, Amazon.com(2013)

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Academic Excellence Award, JNTU Hyderabad (2008-2012)

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