Engineer Design
Resume:
NITIN ROHILLA
Mobile: +91-997******* Address:
House no- 006,
C-block, Parimala trinity,
Boganhalli road, Panathur,
Bangalore.
E-Mail: *********@*****.***
TECHNOLOGY PROFESSIONAL
VLSI Design . Microelectronics . VHDL/VerilogHDL
Objective
< To work in a challenging environment, that provides opportunities to
leverage on my acquired skill set, expertise and experience.
SYNOPSIS
< Progressive 2.11 years of experience as Design and verification Engineer
with Calypto Design Systems, Noida, India from March 2012 to till Date.
< Selected for 7 week (Higher Education Program) training in Mentor
Graphics Noida on "Verification of Electronic Design and Systems using
system Verilog".
< Worked as a BSS Engineer in Geine Technologies India Pvt. Ltd., Gurgaon,
India From Jan 2008 to March 2010
ACADEMIA
Technical & Academic Qualifications:-
Academic Aggregate College University/Board
Percentage Year of passing
M.TECH 79.20% Electronic Kurukshetra
(Microelectronics Science University 2012
& VLSI Design) Department, KU
B.TECH 68% ACEAR, Haryana Kurukshetra
University 2007
AISSCE 60.20% Aggarsain CBSE
Public School, 2003
Kurukshetra
10th 69.2% Aggarsain CBSE
Public School, 2001
Kurukshetra
Technical skills:
< Sound knowledge of HDLS, Verilog/VHDL, System Verilog, UVM and TCL.
< Knowledge of ASIC low power design methodology.
< Hand on experience in using EDA tool like PowerPro, SLEC, Meridian,
Modelsim, DC and RC.
< Front End tools : ModelSim, Active-HDL6.3, FPGA advantage.
< Back End Tools : IC Station (eldonet)
< Device Modelling Tool : Silvaco (Atlas, Deckbuild Interactive
Environment, Tonyplot)
< Process Simulation : Athena
Job Responsibilities:
< Hand on task of implementing the test plan and test cases.
< Development of Verification Environment (VE) / Verification Component
(VC) using System
verilog.
< Hand on experience in creating Verification Environment & Constraint
random test generation in UVM and System Verilog.
< Hand on experience in system verilog assertion based verification.
< Writing tests, functional coverage and assertion coverage and mapping
these to Verification plan.
< Functional verification of the design and achieve verification goals.
< Product engineering work like developing scripts in TCL for stress
testing.
< Validation of various PowerPro Products and features like PowerProCG,
PowerPro MG and power optimization.
< Perform validation activities like unit and stress testing.
< Experience in working multi-geography teams.
CAREER SCAN - Project Details
Calypto Design Systems (March 2012 to till
date )
1. Development of Verification IP for AXI-4 protocol in UVM
Description: - AXI, the third generation of AMBA interface defined in the
AMBA 3
Specification, is targeted at high
performance, high clock frequency
System designs and includes features that
make it suitable for high speed
Sub-micrometer interconnect
< Separate address/control and data phases.
< Support for unaligned data transfers using byte strobes.
< Burst based transactions with only start address issued
< Issuing of multiple outstanding addresses with out of order
response.
Responsibilities: -
< Understood the AXI Protocol specification.
< Prepared the verification plan
< Single master and single slave VIP.
< Burst modes supported are increment, wrap and fixed.
< Data transfer for aligned and unaligned address.
< Constrained random stimulus generation using sequences.
< Functional coverage
2. Verification of Router 1x3 in UVM
Description: - Router is a device that forwards data packets between
computer networks. It is an
OSI layer 3 routing device. Based on a
predefined protocol, this router drives an
incoming Packet to any one among the three
output channels based on the address
field contained in the packet header.
Responsibilities: -
< Developed Architecture of Verification Environment using SV &
UVM.
< Developed of various test cases & verified RTL.
< Generated Functional & Code Coverage for Verification
Signoff.
3. LC3 microcontroller Verification in UVM.
Responsibilities:
1. Verification of un-pipelined LC3 microcontroller in UVM.
2. Create standalone verification environment in UVM for Fetch, Decode
and ALU Block.
3. Verification of Intel blocks with and without power Optimization done
by Powerpro.
4. Conducted functional simulations using Ncsim and ModelSim software
simulator
5. Involved in System Verilog random verification environment, write
directed random templates and assertion based verification.
6. Isolated many critical bugs in the design using the random templates
and running regressions.
Validation of different PowerPro features:-
1. Validation of Multi-Vth
CMOS technologies support the fabrication of transistors with
different threshold voltages (Vth
values). In that case, the cell library can offer two or more
different cells to implement each
logic function with each using a different transistor threshold
voltage. For example, the
library can offer two inverter cells: one using low-Vth transistors
and another using high-Vth
transistor.
Multi_Vth command is used to set the multi_Vth constraints in the
design.My responsibility is to
validate the design by setting different multi_Vth constraints in
verilog and System Verilog.
2. Validation of UPF
UPF is an independent way of annotating a design with power intent
.Load_upf command is
used to read the upf file and help in accurate power analysis and
optimization. My role to
create test cases and validate power no's after varying voltage value
in UPF file.
3. Meridian PowerPro Integration
Meridian is a tool which is being used for generating constraints for
different Powerpro flows.
My job is to verify the correctness of constraints generated from
Meridian and also automate
the same in Powerpro flows.
4. Mixed language
My job is to write test cases using VHDL and system Verilog in a single
design and validate
different construct of VHDL and system Verilog in PowerPro.
5. Validation of Read_Sdc command
Specifying design constraints like power, area e.t.c are tedious for
large customer design. To
make PowerPro to read these constraints read_sdc command is introduced
to help the user to
apply constraints into PowerPro flow.
My responsibility is to read sdc commands through an sdc file and
verify functionality of
different PowerPro flow in Verilog.
6. Validation of Spef command
Capacitance of the signals is a metric to compute power .Read_spef
command is introduced to
read capacitance of signals and accurately compute power for libraries
less than 28nm which
doesn't have wire load models. My role is to compose different
testcases in verilog and check
correct value of capacitance is picked from SPEF file.
Client Details: Calypto Design Systems
Tools : PowerProCG, PowerPro MG
2. Geine Technologies India Pvt. Ltd. (Jan 2008 to March 2010)
Project Description:
. Alarm Monitoring & Troubleshooting on MTS PROJECT AT ZTE ZXSDRB8200
BTS Platform
. Alarm Monitoring for Case of BTS Down & Maintaining SLA and Creating
Trouble Tickets in
major, critical or emergency case.
. Troubleshoot the Problem of BTS CDMA Network using NETNUMEN Remote
login. Fault finding and Repairing of CDMA Base Transceiver Station
(BTS) units using software up gradation.
. Initiate fault clearance procedures for detected alarms via OMC.
. Maintaining SLA & Preparing KPI's on daily as well as weekly basis.
Extra Curricular Activities
< Won 2nd Prize in Technical Quiz Competition in National Level Symposium
(NASET 2010) On "Electronics Technology" organized by Electronic society,
Electronic Science Department, Kurukshetra University, Kurukshetra.
< Participate in Workshop on "Challenges and Opportunities in Analog and
Mixed Signal Design (AMS-2011)" organized by Electronic Science
Department, Kurukshetra University, Kurukshetra.
< Participate in Technical Paper presentation, Technical Quiz, Poster
making competition in National Level Symposium (NASET 2011) On
Electronics Technology organized by Electronic society, Electronic
Science Department, Kurukshetra University, Kurukshetra.
Seminar/Presentation
< Seminar on Polymer Memory during 3rd Semester at Department of Electronic
Science, Kurukshetra University, Kurukshetra.
PERSONAL DOSSIER
Father's Name: Mr Suresh Rohilla
Date of Birth: 20th Jan, 1985
Gender: Male
Nationality/Status: Indian/Unmarried
Language Known: Hindi, English
Passport: H6927580
[NITIN ROHILLA]
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