Project Design

Agasthya Sneha

H.No:**-**-***/*** *************@*****.***

Sitafalmandi, Hyderabad. 970*******

Summary: I am a Graduate student from VIT University, worked as an intern in Intel Corporation,

looking for a well qualified job in the field of VLSI design.

Objective:

To give my best in working for the organisation and become one of the key pla yers in organisation

growth and development.

Education:

Masters in VLSI DESIGN July'12-May'14

Vellore Institute of Technology, VIT University CGPA: 8.51/10

Relevant Courses: VLSI Design Verification and Testing, ASIC Design (physical design), Digital

Electronics, Analog IC, Low Power IC Design.

Bachelors of Engineering, Electrical & Communication Engineering May'08-Apr'12

Jawaharlal Nehru Technological University, Hyderabad, India Secured%=84.1

Relevant Courses: Digital Communications, Analog Communications, Computer Networks, VLSI

Design, C language, Data Structures.

Jun’06-Mar’08

Board of Intermediate Education, Maths, Physics &Chemistry

Narayana Junior college Secured%=93.8

Mar’06

Board of Secondary Education

Vedic Vidyalayam High School Secured%=85

Technical Proficiency:

Cadence virtuoso, Cadence Layout

Editor, Synopsys(design RTL compiler,

EDA Tools & Simulators power compiler) Quartus, Modelsim

HDLs : Verilog, VHDL(basics)

Operating Systems : Windows, Unix.

Programming Languages : C, C++(basics), Keil, perl, TCL.

Areas of Interest:

Digital VLSI Design, Physical Design (ASIC), Verification & Testing and RTL coding.

Internship:

Intern at INTEL India, as HVM test content developer and validate in pre-silicon environment.

Oct’13-May’14

Worked on Broadwell server- Entry level as well as Enterprise level

Project goals include:

Development of HVM content

Validate in pre-silicon environment

Achieve the target Fault Coverage

Academic Projects:

Qualitative HVM Content Development and Validation for Xeon Based Servers

Oct’13-May’14

Project goals include, to develop high quality test content

Achieve the target fault coverage

Maintain DPM

A Faster Floating Point Multiplier Using Dadda Algorithm

Jun ’13-sept’13

Project goals include, a faster floating point multiplication

Multiplier based on Dadda algorithm and final addition is done using hybrid adder.

Design was implemented in Verilog HDL and synthesis is carried out in Altera Quartus II tool.

Delay Elements for Glitch Free Operation

Feb'13-Apr'13

Project goals include, designing the delay elements in order to get glitch free results.

Design was simulated in Cadence Virtuoso using TSMC 45nm CMOS cell library.

Hardware Efficient Processing Elements for Motion Estimation

(ASIC Implementation)

Feb'13-Mar'13

Project goals include, to generate the motion vector.

Design was described in Verilog HDL and synthesized in Cadence RTL Compiler.

Synthesis results are presented for TSMC 45 nm CMOS technology and architecture was

implemented in Cadence SoC encounter tool.

VLSI Architecture for Motion Estimation Based on Diamond Search Algorithm

Aug'12-Nov'12

Project goals include conversion of image frame into binary image also to develop an

efficient VLSI architecture for ME.

Source code was implemented in VerilogHDL.

Software Used: MATLAB, ModelSim, QuartusII.

RF Remote Control Metal Detecting Robot

Jawaharlal Nehru Technological University, Hyderabad, India Jul'11-Oct'11

Project goals include detecting the metals by RF remote control robot.

Source code was written in Embedded-C.

Comparative Study of Image Fusion

Jawaharlal Nehru Technological University, Hyderabad, India Dec'11-Mar'12

Project goals include identifying the best technique to fuse images through fusion algorithms.

Software Used: MATLAB.

Achievements:

SET Conference paper of M.Tech 2nd semester entitled as “Hardware Efficient Processing

Elements for Motion Estimation” has been selected for publication in the International journal

“European Journal of Scientific Research (EJSR).”

Achieved meritorious certificate for securing 2nd topper in UG.

Honors and Certifications:

Secured a C.G.P.A of 9.8/10 for final year project “Comparative Study of Image Fusion ”

Presented technical paper for the conference “aakruthi ‘11”, held at Osmania University,

Hyderabad.

Achieved 1st prize in Throw ball in inter college competition, 2011(Hyderabad).

Achieved 2nd prize in chess and caroms in college competition, 2009, 2011 (Hyderabad).

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