CURRICULUM VITAE

Name: Prakhar Tandon Gender: Male

Date of Birth: 22/12/1989 Nationality: Indian

Contact No: 964******* E-Mail: acgw3y@r.postjobfree.com

OBJECTIVE:

To obtain a position that will enable me to use my educational background and

strong organizational skills, and also to work well with people that offer

professional growth to my career.

PROFESSIONAL QUALIFICATIONS:

Course : Master of Technology (M.Tech)

Major : VLSI DESIGN (ECE)

University : NIT Jaipur

CGPA : 8.58/10

Year of passing : June, 2014

Course : Bachelor of Technology (B.Tech)

Stream : Electronics & Communication Engineering

Institute : College of Engineering, Roorkee

Percentage : 72.92%

Year of passing : June, 2011

EXPERIENCE:

Work experience of 6 months in Silicon Image India Pvt Ltd. as a Trainee in

the year 2013-14 under the internship of M.Tech (2nd year)

M.TECH THESIS PROJECT AT “SILICON IMAGE INDIA PVT LTD”:

Project Title: Dovelopped HDMI Analyzer and Transmitter by using DVDO

AVLab TPG™ and operated with the computer GUI as HDMI Tx and Rx.

Project description of HDMI Tx:

For Tx, we are sending infoframes (AVI, Audio, SPD, VSIF, Gamut

metadata, ISRC1, ACP) by GUI (user’s computer)

Encoded all of these infoframe and store in a file and send to USB

port of HDMI Tx with specific transaction ID

In the Firmware, we are adding Header bye and required checksum

value and storing in Tx register and Rx register

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Project description of HDMI Rx:

For Rx, we are reading all of the infoframe regoister and send to USB

port of HDMI Rx

Decoding all of these infoframe

Displaying over GUI (user’s computer)

B.TECH INTERNSHIP AT “CEERI PILANI”:

Project Title: “Power loss calculation for Power MOSFET Switching & Design

of Isolated Pulse Generator for 15 kV Pulsar”

Project description: In the first part of the project, the switching waveforms

are analyzed and the total switching loss is calculated after building a MOSFET

(IRFP240) Switching Circuit with RL load on general purpose PCB Board. In

the second part of the project, an isolated gate pulse generator is designed

with the help of multivibrators and isolation is achieved using optical

transmission.

TECHNICAL SKILLS:

Languages: Basics of C, Data Structure, VHDL, VERILOG

Operating System: Microsoft Windows 7, Linux ( Ubuntu)

Synopsys Tools: HSPICE, CosmosScope

Cadence: Virtuoso

Mentor Graphics: ModelSim Simulator

Other: Worked on Firmware and visual studio

ACHIEVEMENTS:

Four times GATE Qualified, GATE 2012 with 99.39 percentile

Achieved the first rank in “ART Competitions”

Achieved the first rank in “G K Competitions” at school level

ACADEMIC PROJECTS:

M.tech 3rd Sem: “Hardware Implementation of RC4 Cipher” using

VERILOG.

Synopsis: In this project, hardware Implementation of RC4 cipher with high

throughput is done using VERILOG. It generates key stream of 1 byte per

clock and xored with plaintext / ciphertext to produce ciphertext / plaintext

at the Tx and Rx side.

M.tech 2nd Sem: “Improvement of Linearity of Gilbert Cell Mixer by using 3rd

order Transconductance cancellation”

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Synopsis: In this project, the linearity of Gilbert cell mixer is improved using

3rd order Transconductance cancellation. Gilbert cell mixer consists of

MOSFET but ideally all of these have nonlinearity and generate unwanted

frequency. So here, the cancellation of 3rd order gm terms is achieved. It has

high effect and improves linearity.

M.Tech 1st Sem: “GCD Computation” using VHDL.

Synopsis: In this Project, greatest common divisor of 2 numbers by using

structural digital circuit is achieved using VHDL.

B.Tech 8th Sem: “ Highly effective security system in oil field using wireless”

Synopsis: In this project, the temperature is sensed to take decision about

fire at remote area and is sent to the HUB for automated safety actions.

EDUCATION:

Qualification Year University/Board Percentage/CGPA

XII 2005 Uttarakhand Board 79.80%

X 2003 Uttarakhand Board 75.50%

HOBBIES:

Sketching

Visiting Historical Places

Playing outdoor games

LANGUAGES KNOWN:

English

Hindi

EXTRA CURRICULAR ACTIVITIES:

Active Contribution in Organization of Seventeenth International Conference

on VLSI Design and Test (VDAT 2013)

Participated in the Workshop on “Analog System Design” organized by

MNIT Jaipur in collaboration with Texas Instruments University

Program and Cranes Software.

Participated in Analog Design Contest organized by MNIT Jaipur in

collaboration with Texas Instruments.

STRENGTH:

Leadership Quality

Adaptability

Confidence

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PERSONAL INFORMATION:

Father's name: Shri Gyanesh Chandra Tandon

Mother's name: Smt. (Dr.) Deepti Sareen

Marital Status: Single

Permanent Address: Puthia ji ka baag

Girital Road

Kashipur, Uttarkhand- 244713

DECLARATION:

I hereby declare that the information furnished above is true to the best of my

knowledge.

Date: Prakhar Tandon

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