Design Engineering

Ekta Agrawal

Pavansut Traders,

Gudhiyari, Raipur, Email: *******@*****.***

C.G, India – 492001 Mobile: +91-975*******

Summary of Qualifications

•Good understanding of the ASIC and FPGA design flow.

•Experience in writing RTL models in Verilog HDL andTestbenches.

•Experience in using industry standard EDA tools for the front-end design and

verification.

•Programming Languages: Proficient in C & C++.

•Assembly Languages:Working knowledge of microprocessor 8085 and 8086.

•Proficient in Digital Electronics.

•Analog electronics.

•Knowledge of unix environment.

•Circuit Simulator:MULTISIM

VLSI Domain Skills

HDLs: Verilog

EDA Tool: Questasim,ISE and XPE.

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Synthesis.

Professional Qualification

Bachelor of Engineering,NIT Raipur, Raipur

Discipline: Electronics & Telecommunication Engineering

CGPA: 8.14

Year: May 2015

Internship Experience

VLSI Projects

AMBA AHB – RTL design

HDL: Verilog

EDA Tools: Modelsim,Questa -Verification Platform, ISE

Implemented the AMBA AHB using Verilog HDL independently

Verified the RTL model using Verilog.

Generated code coverage for the RTL .

Synthesized the design

Dual Port RAM – verification

HDL: Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HDL independently

Verified the RTL module using Verilog

MBIST-RTL Design

HDL: Verilog

EDA Tools: Modelsim, ISE

Architected the design and described the functionality using Verilog HDL.

Verified the RTL model

Synthesized the design

ALU – RTL Design and Verification

HDL: Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Architected the design

Implemented the RTL using Verilog HDL

Verified the RTL using Verilog HDL

Implemented the design on the Spartan, Xilinx FPGA and verified the design on

the board

References

On Request

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