VLSI, ASIC, Physical design, RTL design, Verification and Testing

PARMEETSINGH G JAGYASI

**** ******** ******, *** #*** Los Angeles, CA, 90007 *******@***.*** 213-***-****

https://www.linkedin.com/pub/parmeet-singh/15/245/734

OBJECTIVE

Seeking an Internship/Co-op and Full Time in the field of Electrical Engineering that utilizes my Engineering and

Project Management Skills.

EDUCATIONAL QUALIFICATIONS

• M.S. Electrical Engineering, GPA-3.35/4.0 Expected Graduation-May

2015

University of Southern California

• Bachelor of Engineering in Electronics Engineering, GPA-3.6/4.0 September 2009- May

2013

Mumbai University

• Related Coursework till date:

1) MOS VLSI Circuit design 2) Computer Organization 3) Real Time Computer Systems

4) VLSI System Design I 5) Computer Systems Architecture 6) Programming of System Design 7) VLSI System Design

II 8) Diagnosis and Design of Reliable Digital Systems 9) Nano-Fabrication

INTERNSHIP

• In Reliance Infrastructure under SCADA department for a year (June 2012 to May 2013) and completed a project

on ULTRASONIC VISION SYSTEM which is useful in aerodrome to continuously observe fuel tanks.

• The project is based on use of Ultrasonic Sensor to continuously check the maximum and minimum level of fuel

in the tank. If it crosses the limit, then it immediately alerts by sending a message through GSM. In this communication,

levels are shown on PC display via GUI (graphic user interface).

SOFTWARE SKILLS

• Languages- C/C++, JAVA, Verilog, VHDL, Perl, Unix.

• Software’s- Cadence, Model Sim, MATLAB, Xilinx, Microwind, AutoCAD.

• Operating Systems- Windows (all versions).

• Hardware and Applications- IC 8085,8086,8087,8051, Pic18 and Microsoft Office.

ACADEMIC PROJECT

• MULTI-CYCLE CPU (January 2014 to May 2014)

The Project is based on designing Simple General Purpose Multi-cycle CPU aiming at Optimizing Area, Delay and

Power.

• FULL-CUSTOM DESIGN OF 1K BIT 6-TRANSISTOR SRAM (February 2014)

Designed schematic and layout of a 1024-bit SRAM.

• 64-BIT STATIC ADDER DESIGN (March 2014)

Designed schematic and layout of the basic Gray and Black cells for Kogge Stone. DRC, LVS, Timing analysis from

netlist simulation.

• AUTOMATED PARKING SYSTEM (January 2014 to May 2014)

This Project is based on developing a Software system that receives data about the current occupancy status of a parking

lot.

• 2:1 ARBITER (September 2013 to December 2013)

The Project was based on 2:1 (2 input, 1 output) Arbiter to achieve fair arbitration for two 4-bit data transmitters by

using signals like Ready, Stall for each i/p and o/p and control signals like Reset, Select using Cadence Software.

• DESIGN AND IMPLEMENTATION OF 5-STAGE PIPELINE CPU (October 2013)

Designed datapath and control unit. Implemented the design using RTL coding in Verilog HDL and simulated using

Modelsim.

• COUNTDOWN TIMER (Jan 2012 to May 2012)

The Project was based on Up and Down Counter with a Reset button on it. It consists of a display which gives the details

of up and down counts.

• TRAFFIC LIGHT PROJECT (Jan 2011 to May 2011)

The Project was designed to control 4 way traffic signal which includes Green, Yellow and Red light on each side. It

consists of a Timer which was set and according to it the traffic signal works.

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