Design Engineer
Resume:
`Upendhar Gummula
Santhosh nagar,
Champapet
Email: ************@*****.***
Hyderabad, India - 560076 Mobile:
Career Objective
To work as a VLSI/ASIC Verification/ Design Engineer in an
organization where I can utilize my technical skills for organizational
development and my professional career growth.
Summary of Qualifications
> Good understanding of the ASIC and FPGA design flow
> Experience in writing RTL models in Verilog HDL and Testbenches in
System Verilog
> Very good knowledge in verification methodologies, specially in UVM.
> Experience in using industry standard EDA tools for the front-end design
and verification
VLSI Domain Skills
HDL: Verilog
HVL: SystemVerilog
Verification Methodologies: Coverage Driven Verification
Assertion Based Verification
TB Methodology: UVM
EDA Tool: Questasim and ISE
Domain: ASIC/FPGA Design Flow, Digital Design
methodologies
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Functional
Coverage, Synthesis,
Static Timing Analysis, ABV
Scripting language Perl, Shell (Makefile)
Professional Qualification
Maven Silicon Certified Advanced VLSI Design and Verification course
From Maven Silicon VLSI Design and Training Center, Bangalore
Year: October 2013
Bachelor of Engineering, Scient intstitute of Technology
Jawaharlal Nehru University Hyderabad, Andhra
Pradesh, India
Discipline: Electronics and Communication Engineering
Percentage: 63%
Year: May 2013
H.S.C. (10+2) : Sri Chaitanya Junior Colleage
Andhra Pradesh Higher Secondary Education Board
Percentage: 83% distinction
Year: May 2009
S.S.C. (10) : Little Flower High school
Andhra Pradesh Secondary Education Board
Percentage: 85% distinction
Year: May 2007
Experience
June 2013 - October 2013, Maven Silicon, VLSI Design and Training Center-
Bangalore
VLSI Projects
AMBA AXI 4 Protocol Verification using UVM
HVL: SystemVerilog
Methodology: UVM
EDA Tools: Modelsim, QuestaSim -- Verification Platform
Description: The AMBA AXI protocol is targeted at high-performance, high-
frequency system and includes a number of features that make it suitable
for a high-speed submicron interconnects. The AXI protocol is burst-based.
Every transaction has address and control information on the address
channel that describes the nature of the data to be transferred. The data
is transferred between master and slave using a write data channel to the
slave or a read data channel to the master.
> Architected the class based verification environment using UVM.
> Verified the protocol using class based UVM Test bench.
> Verified the master-slave signal transactions.
> Generated functional coverage for the verification sign-off
Router 1x3 - RTL Verification using UVM
HVL: SystemVerilog
Methodology: UVM
EDA Tools: Modelsim, Questa -- Verification Platform and ISE
Description: The router accepts data packets on a single 8-bit port called
data and routes the packets to one of the three output channels,
channel0, channel1 and channel2.
.
> Architected the class based verification environment using UVM.
> Verified the RTL model using class based UVM TB.
> Generated functional and code coverage for the RTL verification sign-
off
Dual Port RAM - RTL Design and verification
HDL: Verilog
HVL: System Verilog
EDA Tools: Modelsim, QuestaSim - Verification Platform and ISE
> Implemented the Dual Port Ram using Verilog HDL independently
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using System Verilog
> Generated functional and code coverage for the RTL verification sign-
off
RAM SOC - Verification
HVL: System Verilog
Methodology: UVM
EDA Tools: Modelsim, Questa - Verification Platform and ISE
Description: The Design under Test (DUT) for this verification test bench
is RAM SOC.
It includes four instances of 4096 x 64 RAM chip
> Architected the class based verification environment using UVM
methodology.
> Verified the RTL module using the UVM class based TB.
> Generated functional and code coverage for the RTL verification sign-
off
Design project:
Router 1x3 - RTL design
HDL: Verilog
HVL: Verilog
EDA Tools: Modesim, ISE design tool.
Description: The router accepts data packets on a single 8-bit port called
data and routes the packets to one of the three output channels, channel0,
channel1 and channel2.
> Architected the design and described the functionality using Verilog
HDL.
> Verified the RTL model using Verilog TB.
> Generated code coverage for the RTL verification sign-off
> Synthesized the design
Engineering Project
Design of an AMBA-Advanced High Performance Bus (AHB) Protocol IP Block
HDL: Verilog
EDA Tools: Modelsim
Description: The AHB (Advanced High- performance Bus) is a high performance
bus in (Advanced Microcontroller Bus Architecture) family. This AHB can be
used in high clock frequency system modules. The AHB acts as the High
performance system backbone bus. AHB supports the efficient connection of
processors, on chip memories and off-chip external memory interfaces with
low-power peripheral macros cell functions.
Personal Details:
V Name :- Upendhar Gummula
V Nationality :- Indian
V Languages Known :- English, Hindi, Gujarati.
V Date of Birth :- 15th April,1992
V Blood Group :- O+ve
V Address: :- H.no 1-31/a, Ramannapet, Morthad,
Nizamabad,
Telangana, India-503225
Declaration
I hereby declare that the information given here with is correct to
best of my knowledge and I will responsible for any discrepancy.
Place: Bangalore Upendhar
Gummula
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