Project Design

Objective

To be a part of growing organizations, that provides

N ITHYA.N

opportunities for continuous learning and professional

g rowth in a thoroughly motivating work environment

Personal Data:

and also to contribute myself as a part of the team

t hat excels in work towards growth of the

Permanent Address:

organization.

D/O K.Natarajan,

No:15,Kasuvareddypatty,

Educational Profile

T haramangalam (PO),

Completed M .E f rom K .S.Rangasamy College of

Omalur (TK),

T echnology i n the discipline of V LS I Design f rom

Salem-636502.

A nna University Chennai w ith an aggregate of 7.2

C GPA (till 3 rd semester) i n the year of 2014.

Contact Number:

Mobile : 888-***-**** Completed B.E f rom A nna University of

T echnology Coimbatore C ampus i n the discipline of

Email id:

E lectronics and Communication Engineering i n

***********@*****.***,

t he year of 2011 w ith an aggregate of 8.47 CGPA.

Personal Details:

Completed D iploma f rom K .S.R.Institute of

Sex : Female T echnology f rom T amilnadu State Board i n the

Date of Bir th : 06.07.1990 year of 2008 with an aggregate of 87.92%.

Languages : English,

Tamil.

Completed SSLC f rom Government Girls H igher

Mari tal Status : Single

Seconda ry School, T haramangalam from

Nationality : Indian

T amilnadu State Board i n the year of 2005 with an

aggregate of 82.4 %.

s

Executive Summary

Energetic and self-motivated, quick learner and with

good mathematics background. At ease in high stress

and fast-paced environments requi ring the ability to

effectively handle senior level responsibilities.

In terested in learning new technologies.

Have good presentation skills, attention to detail with

Co-Curricular activity

Participated Two Days National Level Workshop On “ Essentials of

F PGA and Rapid P rototyping With Xilinx FPGA ” at Sri Shakthi

I nsti tute of Engineering And Technology, Coimbatore.

Participated Two Days National Level Workshop On “ V H D L

p rogramming and practice ” at Bannari Amman Institu te of Technology,

Sathyamangalam.

Presented a Paper In “ I E EE I n te rnational Conference On I CBD M-

2014” at Noorul Islam University, Kanyakumari.

Area of In terest

Digital Electronics

ASIC Design

In plant Training Undergone

Undergone In plant Training at “ BSNL’’ Mettur.

Projects

PG P roject:

T i tle: Pulse width Controlled Clock Generator for Low Power SOC Applications

T echnology: V LSI Design.

Software Used : X ilinx I SE and MO DE L SI M 6.3f

O bjective: A fast-locking pulsewidth-controlled clock generator (PWCCG) based

on delay locked loop is proposed in this project with the help of coarse and fine delay

l ines and a t ime-to-digital detector. A new duty cycle setting circuit is also presented

i n this project which decides the preferred output duty cycle.

U G P roject:

T i tle: I mproved T ransition Fault Coverage in Sequential Circuits

D escription: “HAZARD BASED DE TECT ION M E T HO D” is used to increase

t he speed

and fault coverage of system.

Software Used : X ilinx I SE and MO DE L SI M 6.3f

O bjective: T he main objective of this project is to overcome the drawbacks of

conventional detection method. The Principle goal of testing would thus to be check

t he manufactured product completely making sure that it function according to i ts

requirements and detect malfunction and defects in product.

P ersonal strength and precise

P ersonal strength

Punctual and well disciplined.

Sincere and Honest.

Thirst for knowledge and willingness to learn.

Personal P recise

Enthusiastic and hardworking with good communication skill.

In terested in learning recent technologies.

Ability to learn quickly and to implement it effectively.

In terested to work in challenging environment that would help in

adding value to every study or project that I am a part of it.

Declaration

I hereby declare that the above-furnished information’s are t rue to the

best of my knowledge and belief.

P lace:

[ N.Nithya ]

Date: 29th December 2014

Contact this candidate