Design Engineer

SANKET GAJJAR

Phone: +91-972******* (L) 079********; Email: ************@*******.**

SYNOPSIS

To give my best in my professional pursuit for overall benefit and growth of the company that I serve by facing the

challenges. I will show my calibre and gain some experience and I can increase my leadership abilities through

regularly encountering and solving problems.

Good Analytical abilities Flexible

Quick Learner Team Player

CORE COMPETENCIES

Ability to understand RTL Design in Verilog

RTL Simulations and Debug

Ability to develop UVM based Verification environment

Knowledge in SoC Verification flow

TECHNICAL SKILLS

Languages: C, C++, VHDL, Verilog, SystemVerilog

Tools: Synopsys® VCS, Cadence™ NCsim, Xilinx ISE, LATEX

Verification Methodology: UVM

Assertions: SystemVerilog

Scripting: Shell

Protocol: DDR

INTERNSHIP

(17thJune‘13 – 16th June ‘14)

Organization: Freescale Semiconductor, Noida

Responsibilities:

Worked with FAM verification team

Project Handled:

1. Functional Verification of DDR3 IP Memory Controller

Understand DDR Protocol and to aid in developing verification environment using SystemVerilog UVM class

based environment.

Design Register Abstraction Layer and develop testcases for the same.

Developed Concurrent variable assertion to perform automated checks on varying Latency value for

testcase.

2. Development of BIST test patterns for LMTV SoC

SystemVerilog based testbench to generate test pattern for two port RAM instances and ROM instances

with different test algorithm as per requirement of client.

3. Validation of Data Management tool “STINGRAY” for SoC designs

Development of testcases using shell script to run the regression for different encapsulation of various

frontend and backend tools as per features update and tickets files.

EDUCATIONAL CREDENTIALS

M.Tech (VLSI Design) from Nirma University, Ahmedabad in 2014 with CPI 8.73/10 (i.e. 82.3%)

B.E (Electronics & Communication) from LDRP Institute of Technology and Research, Gandhinagar in 2011 with

Aggregate 72.3%

H.S.C from Gujarat State Board in 2007 with 71.4%

S.S.C from Gujarat State Board in 2005 with 80.4%

ACADEMIC PROJECTS

“Design and Implementation of 8-bit ALU” during M.Tech 2nd semester

Aim of to develop RTL coding for 8-bit ALU using VHDL language on Xilinx ISE Simulator and it

was design using VHDL packages to avoid complexity of in single design.

“Sequence Detector from specification to layout” M.Tech 2nd semester.

Design 101 sequence detector from spec to layout. Design was done in VHDL language and layout

was made in MICROWIND using 32nm technology.

Developed “PIPELINED FIR Filter” during B.E 8th semester.

Aim of project was to design Pipelined FIR filter using Verilog and compared with normal FIR

structure.

PERSONAL DETAILS

4th September, 1990

Date of Birth:

Permanent Address: D/2 Kalptaru Flats, Opp. Gita School, Ranip, Ahmedabad-382480, Gujarat

Languages Known: English, Hindi & Gujarati

Location Preference: Anywhere in India

Reference:

Mrs. Nandini Mudgil Mr. Rohit Srivastava

FAM Manager, Sr. Lead Design Engineer,

Freescale Semiconductor Pvt. Ltd. Samsung Electronics, Korea

Email: *******.******@*********.*** Email: ******.**********@*****.***

(Sanket Gajjar)

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