verilog,system verilog,uvm

RESUME

G.GANGI REDDY Email Id : ******************@*****.***

Mobile No :+91-973*******

CAREER OBJECTIVE:

To accept a challenging role in a reputed organization where, I can contribute my technical,

professional, innovation skills and leadership qualities.

ACADEMIC QUALIFICATION:

Course Board/University Name of the Institution Year of Percentage

Passing

B. Tech. JNTU (Ananthapur). Kottam Karunakara Reddy 2013 71.58

Engineering College,

(E.C.E.)

Kurnool.

Intermediate Board of Intermediate, Nalanda Junior College 2009 82

A.P. (Ananthapur).

Secondary Board of Secondary Vignan High School(O.D.C) 2007 78

School Education, A.P.

Skills:

Hardware Languages : VERILOG, System Verilog, UVM.

Software languages : C, Basic OOP’s.

Hardware design tools : Xilinx (FPGA

boards),MentorGraphics(QuestaSim&ModelSim).

Script languages : PERL.

Operating Systems : Windows, Linux.

Certified courses:

Maven Silicon Certified Advanced VLSI Design and Verification coursefrom Maven Silicon

Softech Pvt Ltd., VLSI Design and Training Center, Bangalore.

PROJECTS:

FIRE CONTROL ROBOT WITH HIGH PRESSURE WATER SPLINKER.

Project Role:Team leader

Domain:Embedded system

Description:In this project if any fire accidents occur the sensor sense automatically.Robot

splinks the water on fire accidents.RF control robot used AT89S52MCU. when the robot is

moving on a surface.It can be used any type of industries,homes,chemical labs e.t.c.

VLSI Projects

:

Title: Router 1x3 – RTL design and Verification

HDL: Verilog.

HVL: System Verilog (UVM).

EDA Tools: Questa – Verification Platform and Xilinx ISE.

The router accepts data packets on a single 8-bit port called data and routes the packets to one of the

three output channels, channel0, channel1 and channel2.

Architected the design and described the functionality using Verilog HDL.

Architected the class based verification environment using system Verilog.

Verified the RTL model usingUVM methodology in SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off.

Synthesized the design.

GPIO – Verification

HVL : System Verilog

TB Methodology: UVM

EDA Tools: Questasim

Description: General purpose I/Os used in SoC

Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

SPI Controller Core - Verification

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim

Description: The SPI IP core provides serial communication capabilities with external device

of variable length of transfer word. This core can be configured to connect with 32 slaves.

Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

STRENGTHS:

• Good planning and event management skills.

• Adaptability to new environment.

• Positive attitude, hardworking, confident and dedicative.

PERSONAL INFORMATION:

Name :G. Gangi Reddy

•

Date of Birth :04-06-1992

•

Father’s Name :Mr. G. Nagi Reddy

•

Permanent Address :H. No. 2-21, Enagaluru(V&P),O.D.C.(M), Ananthapur(Dist)

•

Languages Known :Telugu, English

•

Hobbies :Playing Cricketand Solving Sudoku puzzles.

•

I hereby declare that all the information furnished above is true and correct to

the best of my knowledge.

Place :Banglore.

Date : (G. Gangi Reddy)

Contact this candidate