Engineer High School
Resume:
RESUME
SATISH KUMAR.G
Address:
Beside Dharmashala, Email:
**************@*****.***
Ghatkesar (V & M), Contact No:
Hyderabad.
CAREER OBJECTIVE:
Seeking an opportunity with an organization that offers professional
and challenging environment where my skills, experience and technical
knowledge are utilized for organizational and personal growth.
CAREER GRAPH:
ENGINEER: RELIABLE TECHNO SYSTEMS PVT. LTD
. Since Mar 2013 to till date
. Key Projects Handled:
. Verification & Implementation of digital HMS timer.
. Verification & Implementation of RC4 Stream Cipher Algorithm.
. WAR HEAD, RCI HYDERABAD.
. Rotary Electro Mechanical Actuator (REMA), RCI HYDERABAD.
. Responsibilities:
. Accountable for understanding the customer requirement,
conceptualization for the projects and deciding viability of the
system.
. Preparation of Schematics, BOM and Layout.
. Preparation of firmware requirement documents.
. DC analysis, Thermal analysis documents, Functional Verification by
simulation and system delivery.
. Preparation of Design documents, Layout guidelines & Test Report
Summary documents.
. Involved in testing of VHDL codes using XILINX ISE and QUESTA SIM.
. Hardware debugging and system level test.
. Integration and Environmental testing.
. Tools Used:
. Modelsim
. Xilinx ISE
Engineer - Strategic Electronic Division (R & D): ECIL
. Since Aug 2010 to Aug 2012
. Projects Handled:
. Implementation of Digital Down Converter (SEEKER), Brahmos
Hyderabad.
. Implementation of MMI and Intermodule Communication between V/UHF.
. BrahMos Missile Weapon complex, Brahmos Hyderabad.
. Responsibilities:
* Preparing & monitoring the in line process.
* Strategy planning of work force with available resources.
* Ensure productivity with quality in scheduled time lines.
* Exposure in product development/process development.
SCHOLASTIC PORTFOLIO:
* M.Tech (VLSI System Design) 2014 passes out from Vathsalya Institute
of Science and Technology, JNTU, having 73%.
* B.Tech (Electronics and Communication Engineering) 2010 passes out
from Samskruti College of Engineering & Technology, JNTU, having 63%.
* Intermediate (MPC) 2006 passes out from Ratna junior College (Board of
Intermediate Education, AP), having 66%.
* SSC 2004 passes out from Vignan's high School (Board of Secondary
Education, AP), having 66%.
COMPUTER PROFICIENCIES:
. EDA Tools : Modelsim, Xilinx ISE, Questasim.
. Hardware Description Languages : VHDL, Verilog, System-Verilog.
. Basic Language : C, PERL.
. Operating Systems : Linux, Windows.
PROFESSIONAL SUMMARY:
. Good team player.
. Good hands on VHDL, Verilog, System Verilog.
. Involved in testing of VHDL codes using XILINX ISE and QUESTA SIM.
. A good knowledge on Digital and Analog VLSI design process.
. Experience on ASIC Design and verification.
. A good knowledge on gate level simulation, FSM Design and debugging
skills.
PERSONAL STRENGTHS:
* Positive attitude.
* Willingness to learn and ability to work hard.
* Ability to work in group as well as independently with minimal
supervision.
* Ability to accept challenges and fulfilling the same.
* Good leadership qualities.
* Able to coordinate several tasks simultaneously.
PERSONAL DETAILS:
Father Name : G.Yadagiri
Date of Birth : August 4th 1988
Sex : Male
Values : Deterministic, Jovial &
Dedicative
Nationality : Indian
Marital Status : Single
Languages Known : English, Telugu, and Hindi
Address : HNO: 6-155, Ghatkesar (V&M), RR Dist, AP, 501
301
DECLERATION:
I hereby declare that the above given particulars are true to the best
of my knowledge and belief.
Date: Regards,
Place: (G SATISH
KUMAR)[pic]
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