Fresher with experience in EDA tools for 1year

ARUNKUMAR V

Sri Bhagyalakshmi PG, *th Main Road, Maruthi Nagar,Madiwala, Bengaluru,

Karnataka. Pin-560068, INDIA

Contact: +917*********; Email: *********@*****.***

PROFILE SUMMARY

. Hands-on experience on Verilog and VHDL programming, Cadence tools in

180nm&90nm technology and Cadence Virtuoso Schematic editor, analog

design environment.

. Gained significant exposure in VLSI Systems and worked in laboratories

for past 12 months.

. Accented with the latest trends and techniques of the field, completed

M.E VLSI Design in R.M.K Engineering College, Anna University, Chennai

with CGPA 8.89

. Successfully completed academic projects on Design and Implementation

of Delay Lock Loop.

. Conceptually strong with an innovative and analytical approach to the

work with an eye for detail. Enriched with the ability to learn new

concepts & technology within a short span of time.

TECHNICAL SKILLS

Programming languages : Verilog HDL, VHDL, C, C++, MATLAB

ASIC Design Tools : Cadence RTL

Compiler, SoC Encounter

Synopsys Design Compiler

ASIC Testing Tool : Tetramax

Mixed Signal Simulation : Cadence Virtuoso

schematic editor

Functional Verification Tools : Model Sim.

Synthesis Tools : Xilinx ISE

Scripting language : Tcl, Perl

Hardware Implementation : Spartan 3, 3E

Analog Simulation : Pspice

Antenna Tools : HFSS, IE3D

ACADEMIC PROJECT WORK

. Design and Implementation of Delay Lock Loop

Tools Used: Cadence Virtuoso schematic editor, analog design environment

Technology Used: UMC 90nm, gpdk 180nm

Analysis: Transient, PNOISE, PSS analysis

Description: DLL is preferred because of its better stability, minimum

jitter and fast locking time and it can be used in clock and data recovery

circuits and in Wireless systems. The proposed work is to enhance the

flexibility of DLL architecture. This architecture has advantages of less

area, low power, low voltage and low phase noise. Also good stability can

be obtained in this design. The circuit level design is presented and

simulation result confirms the analytical predictions.

. Design and Analysis of Penta-Band Fractal Tail end Microstrip Antenna

for LTE Applications

Tools Used: HFSS, IE3D

Description: A novel design technique for enhancing bandwidth that improves

the performance of a microstrip antenna for LTE is proposed. The proposed

antenna has an operating range of 0.7 - 4GHz for Long Term Evolution (LTE)

handsets. The Simulation of this microstrip patch antenna was did on High

Frequency Structural Stimulator (HFSS) software and the simulated results

gave effective return loss, bandwidth and gain. It has been fabricated and

tested using Vector Network Analyzer (VNA) which widely covers five bands

within 4GHz.

. Improving Robustness Against RS Steganalysis Using Particle Swarm

Optimization

Tools Used: Matlab

Description: The most notable steganalysis algorithm is the RS attack which

detects the steg-message by the statistic analysis of pixel values. A new

method based on particle swarm optimization is proposed to improve its

robustness against RS stegnalysis. After embedding the pixel values of the

steg-image are modified by the PSO algorithm to keep their statistic

characters. The image quality is maintained and the result demonstrates

that the proposed algorithm provides improved secrecy against RS

steganalysis with visual quality.

. Evaluation of fault coverage as the metric for different faults in

VLSI circuits using 2D-LFSR

Tools Used: Design Vision, Tetramax

Description: Test patterns were generated using ATPG (Automatic Test

Pattern Generation) and faults were inserted in the netlist file generated

using DFT (Design for Test). Here ATPG is achieved using the combination of

design compiler and Tetramax. Fault coverage and test patterns were

generated. It was observed that neither a comprehensive functional

verification sequence nor a sequence with high stuck-at fault coverage

gives high transition fault coverage for sequential circuits. A customized

2D- LFSR algorithm is used to find the fault coverage and pattern used to

detect the faults.

AREA OF INTEREST

. VLSI Design Techniques.

. ASIC Design

PUBLICATIONS

. "Improving Robustness against RS Steganalysis Using Particle Swarm

Optimization" (International IEEE Conference on Computational

Intelligence and Communication Networks, 2011)

. "Error Detection and Correction in Embedded Memories Using Cyclic

Codes and Power Reduction Techniques" (National Conference on

Emerging Trends in Networking, Automation and Control Technologies,

2013)

. "Evaluation of fault coverage as the metric for different faults in

VLSI circuits using 2D-LFSR" (International conference on Nano

Electronics sciences and Technology, 2014)

. "Design and Implementation of Delay Lock Loop" (National Conference

On Modern Electronics And Signal Processing, 2014)

EDUCATION

Degree: M.E. (VLSI R.M.K Engineering College, 2014 8.89

Design) Chennai

Degree: B.E. University College of 2012 7.93

(Electronics and Engineering, Tindivanam

Communication (Anna University, Chennai)

Engineering)

Class XII: State Board Cluny Matric Hr Sec School, 2008 87

Devikapuram

Class X: Matriculation Cluny Matric Hr Sec School, 2006 83

Devikapuram

ACADEMIC ACHIEVEMENTS & CO-CURRICULAR ACTIVITIES

. Presented Paper in IEEE International Conference on Computational

Intelligence and Communication Networks.

. Presented Paper in International conference on Nano Electronics

sciences and Technology.

. Presented Paper in National Conference on Emerging Trends in

Networking, Automation and Control Technologies.

. Presented Paper in National Conference On Modern Electronics And

Signal Processing.

. President of ELECTROKOM Association in undergraduate course and

conducted symposiums.

. President of Mathematics association in school.

. Represented as College team Captain in Zonal level Cricket tournament.

PERSONAL DETAILS

Nationality : Indian

Marital Status : Single

Date of Birth : 03.10.1990

Father's Name : Velumani A

Sex : Male

Hobbies : Travelling, Listening music

Linguistic Proficiency : English, Tamil

I hereby declare that all the details furnished above are true and correct

to the best of my knowledge and belief.

(ARUNKUMAR

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