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VHDL & Verilog Programming

Location:
India
Posted:
October 01, 2014

Contact this candidate

Resume:

MURTUZA JEERANWALA

Phone: +918*********

Email: ******.****@*****.***

Career Objective

To be a part of reputed organization where in my knowledge and skills can

be utilized optimally contributing to the growth of organization and hence

being successful in long run.

Academic Details

Course Specialization College/School University/Boar Year of Percentage

d Passing

M.TECH ELECTRONICS(VLSI BVDU,COE, Pune Bharati Pursuing 1st sem-6.84

DESIGN) Vidypeeth (2014)

University 2nd sem-6.89,Pune

3rd sem-8.19

4th sem-10

Project Viva

awaited

B.E. ELECTRONICS AND B.I.T.S, Bhopal R.G.P.V, Bhopal 2012 76.44%

COMMUNICATIONS (Distn)

H.S.C. P.C.M Agarwal Public C.B.S.E Board 2008 65%

School,Indore

(M.P.)

S.S.C - Carmel Convent C.B.S.E Board 2006 76%

School,

Neemuch (M.P)

Skills

> Languages : C& C++ Programming, Basic of VHDL Verilog.

> Tools : Codeblocks, Microsoft Visual Studio,

XILINX, Modelsim.

> Interest : Digital Electronics, Data Communication,

A/D Communication

> Target Technology: FPGA.

Trainings Undergone

> Application of Analog and Digital Telephony at Neemuch.

Projects Undertaken

> Implementation of OFDM based IEEE 802.11a Transreciever on FPGA

(M.Tech project)

The project aims at design of digital OFDM Transreciever by defining

the hardware in the form Hardware Description Language (HDL)

> Wireless Energy Meter(Major Project of B.E)

Projects aims at the design and implementation of an embedded system

module for calculating power consumption at one place and wirelessly

transmitting readings to base station.

Achievements and Extra Curricular Activities

> Presented a paper on "Study of OFDM implementation on FPGA" in

National conference on Advance Technologies for secured Communication

Using 4G&LTE

> Presented paper on Bluetooth-An Emerging Technology in 6 SIGMA MCA'09

at LNCT, Bhopal.

> Participated in QUIZ CONTEST and got First prize at BITS, Bhopal.

> Presented a paper on VLSI DESIGN and got First prize at BITS, Bhopal.

Personal Information

Permanent Address - Flat No 304 B-wing Manish Darshan, Fatima Nagar

Pune-411013

Father's Name - Mr. Zakiuddin Jeeranwala

Mother's Name - Mrs. Hussaina Jeeranwala

DOB - 2nd May 1990

Passport No - M1781517

Hobbies & Interests - Travelling, Listening to Music, Playing Cricket and

keeping its

Statistics.

Strength - Politeness, Adaptability, Smart worker.

Languages Known

> English, Hindi, Gujarati &Urdu.

Declaration

I hereby declare that the above-mentioned information is correct I bear the

responsibility for the correctness of the above-mentioned particulars.

Date--

Place--

MURTUZA JEERANWALA



Contact this candidate