M.Tech VLSI Design
Resume:
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Mobile: +91-814*******
SWAPNIL DURWAS NINAWE E-mail:
VLSI Design, ***************@*****.***
National Institute of Technology, Karnataka. DoB :October 22, 1989
Areas of Interest
Digital Design, VLSI Backend Design, Programing Languages (VHDL, Verilog).
Examination University Institute Year CGPA/
%
M.Tech (VLSI Design) NITK, Surathkal NITK, Surathkal 2014 9.03
B. Tech (Elec. & Telecom.) University of Mumbai R.A.I.T., Nerul, Navi Mumbai 2011 71.95
XIIth Maharashtra State Board Shivaji Science College, Nagpur 2007 84.33
Xth Maharashtra State Board Sanjuba High School, Nagpur 2005 90.67
Technical Skill
o Programming Languages: VHDL, Verilog.
o Scripting Language: Perl
o EDA Tools: ModelSim, Xilinx ISE, Electric.
o VLSI Tools: Design Compiler, IC Compiler.
Internship at Intel (May 2013 – May 2014)
o Optimization and Convergence of complex design through RTL to GDSII flow (Synthesis, Floorplan,
Placement and Routing, Clock Tree Synthesis) in SoC Design by using Synopsys Design Compiler, IC
Compiler and Primetime with Hardware Integration Team at Intel Corporation, Bangalore
Responsible to make a utility using C-shell and Perl which provides a single platform to synthesize
every new RTL release model and to provide feedback on RTL quality by monitoring all the
necessary data checks. This helps to enhance the process of Backend to Frontend handoff. This
utility is generic and hence it can be easily portable to any kind of project.
Responsible to make a utility using Tcl which serves the purpose of ICC automation for performance
metrics to analyze the areas of improvements for next SoC releases.
M.Tech Mini Projects
o Implementation of 6 bit Flash ADC using LT-Spice
Basic circuit of 6 bit Flash ADC consists of current mirror, Differential Amplifier followed by Latch circuit.
All 64 comparators are worked on different threshold voltage.
Threshold voltage is controlled by the current passing through the transistor of Differential amplifier by
varying the current from current mirror transistors for fine tuning and also varying the fingers of the two
differential amplifier transistors for coarse tuning.
o Implementation of KL-Algorithm for Partitioning in Perl
Text files are used to provide inputs and also to store the outputs.
Data Structure used: Arrays and Hashes.
Algorithm extended to K-way partitioning.
Further it is also extended for different weight edges.
o Implementation of RISC Processor on FPGA using VHDL
Implemented using VHDL on a FPGA Xilinx Spartan 3E kit.
16 bit 'R' and 'I' instruction formats is used.
Most of the MIPS instructions are supported like Load, Store, Arithmetic (ADD, ADDi, SUB, SUBi), logical
(AND, OR, XOR, NAND, NOR, NOT), BRANCH instructions in multiple clock cycles.
The functionality of design is verified by downloading code in Xilinx FPGA Spartan 3E starter board and
observing the signal in Chipscope
The fetch stage has longest clock cycle of 7.123 ns, so maximum frequency of operation is 140.4 MHz
o Implementation of 4 bit ALU schematic and layout using Electric Tool.
Schematic and layout of 4 bit ALU is implemented using Electric Tool.
Verified the 4 bit ALU with spice code.
Specification: Total Delay: 0.39ns; Average Power Consumptio n: 0.359uW; Total Area: 0.049 (mm)2.
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B. Tech Project
o Moving Person Tracking System Using RFID with GSM module
Description: This project is based on wireless communication using RFID technology, this project used
in conjunction with an automated attendance monitoring system to monitor attendance of student or any
other company employee need to be tracked.
Relevant Courses
o Digital IC Design
o Analog IC Design
o VLSI Design Automation
o Computer Architecture
Extra-Curricular Activities
o Won the second prize in the Planomenia of Technow-2k9 conducted by CSI RAIT.
o Won the second price in the event TECHQUIZ of Techmate conducted by CSI RAIT.
o Qualified for second round in the event Techxenia conducted by CSI RAIT.
Volunteered the cultural event “Kalarag” in 2009-2010 at RAIT.
o
Other Interest
o Playing Cricket, Listening Music.
References
REFERENCE 1 REFERENCE 2
Name: Dr. T Laxminidhi Name: Dr. Aparna P
Designation: Associate Professor at NITK. Designation: Associate Professor at NITK.
E-mail address: ************@*****.*** E-mail address: *.************@*****.***
Phone: 098********
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