Engineer Design

PLOT.NO:***,

C SARITHA

S.K.D.NAGAR, VANASTHALIPURAM, +91-814*******

HYDERABAD, INDIA, 500070.

********.*****@*****.***

SUMMARY

Design Engineer with 2years of experience in Physical design.Have been working and responsible for independent planning and

execution of PNR block level designs.Experienced in parasitic extraction,post layout timing closure and physical verification.Core

strengths in:

• Good at designing blocks based on Cadence using Encounter.

• Hands-on experience in working with 40nm,65nm technology nodes.

• Efficient in data flow diagram based floor plan, congestion aware placement, timing aware cts, and resource concerned routing.

• Efficient in power planning based on IR drop analysis.

• Proficiency in analyzing timing reports and fixing timing and design violations.

• Efficient in using TCL for extracting required information and making automation in the entire design flow.

• Skilled at performing Physical verification.

Proficiency in SI-analysis, Crosstalk avoidance, and handling ECO’s routes.

•

• Good in CMOS basics and IC fabrication process

TECHNICAL SKILLS

Operating Systems Windows 2000/XP/7/8

Programming Languages C,Matlab,Scilab,verilog.

RTL Complier Logic Sysnthesis

EDA Tools Experience:

Static Timing Analysis Encounter Timing System

Physical Design Cadence, Soc Encounter

Extraction Q-RCXT

Physical Verification Aussura

EDUCATION / TRAINING

• PG Diploma in Physical Design, june 2012 from Institute of silicon systems

• M.Tech in VLSI(System Design),Dec 2012 from JNTU Hyderabad with percentage scored 75.00%

• B.Tech in Electronics and Communication Engineering,May 2010 from JNTU Hyderabad with percentage scored 74.25%

• Intermediate May 2006 from Nalanda Junior College Hyderabad with percentage scored 85%.

• SSC, May 2004 from Geetanjali public School with percentage scored 77.5%.

PROFESSIONAL EXPERIENCE

Project1 Physical Implementation and Timing closure of Rectilinear ASIC block

Tools Encounter, Q-RC, ETS.

• 130nm Technology

Block Description

• 34 Macros and 0.9 million gates

• Clock Frequency of 300 MHz

SARITHA 1

• Area of 1.3 Sq.mm

• 7 metal layer process

Responsibilities The responsibility assigned was to deliver the rectilinear block after performing the entire pd flow

with timing clean and error free. The challenge faced was during power planning, timing fixing and

Congestion reduction to achieve maximum area reduction. My major responsibilities also includes

• Floor planning and power planning in Soc Encounter.

• Placement, CTS and Routing by Encounter.

• Extraction by QRC-XT .

• Timing analysis by ETS and making changes in Soc Encounter.

• Fixed LVS Shorts & DRC in Soc Encounter & verified the same in Aussura.

Project2 Physical Implementation and Timing closure of ASIC block

Tools Soc Encounter, Q-RC, Ets, Aussura.

•

Block Description 90nm Technology

• 12 Macros and Approximately 29k gates

• Clock Frequency of 200 MHz

• Area of 1.5 Sq.mm

• 5 metal layer process

Responsibilities My responsibility was to deliver the block with timing closed and physically verified, it involved

me in entire physical design flow and worked till the final stage. The challenges was to meet the

timing across all corners in very tight schedule, also involved in Formal verification and SI

analysis. My major responsibilities include

• Floor planning and P&R Routing using Soc Encounter.

• Parasitic extraction using QRC-XT for worst & best corners.

• Timing analysis by Encounter Timing System.

• ECO changes in Soc Encounter after fixing timing violation in Ets.

• Fixed LVS Shorts & DRC in Soc Encounter & verified the same in

Aussura.

Project3 Physical Implementation and Timing closure of ASIC block

Tools Soc Encounter, Q-RC, Ets, Aussura.

•

Block Description 130nm Technology

• 12 Macros and Approximately 12k gates

• Clock Frequency of 150 MHz

• Area of 1.5 Sq.mm

• 5 metal layer process

Responsibilities My responsibility was to deliver the block with timing closed and physically verified, it involved

me in entire physical design flow and worked till the final stage. The challenges was to meet the

timing across all corners in very tight schedule, also involved in Formal verification and SI

analysis. My major responsibilities include

• Floor planning and P&R Routing using Soc Encounter.

• Parasitic extraction using QRC-XT for worst & best corners.

• Timing analysis by Encounter Timing System.

• ECO changes in Soc Encounter after fixing timing violation in Ets.

• Fixed LVS Shorts & DRC in Soc Encounter & verified the same in

SARITHA 2

Aussura.

Project4 Physical Verification of a ASIC block

Tools Soc Encounter, Aussura.

• 90nm Technology

Block Description

• 6 metal layer process

Responsibilities My responsibility is to deliver the block physically verified by clearing the errors. The block had

critical routing resources faced several overlaps, shorts and minimum enclosures in the design. My

major responsibilities include

Fixing DRC & LVS in Soc Encounter & verified the same in Assura.

PERSONAL DETAILS

Name C Saritha

Father Name C Balaiah

DOB 12-Sep-1988

Languages English and Telugu

Marital Status Single

SARITHA 3

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