Cadence,RF Cmos

C hanakya.Dharani

Address for Communication

H.no 19/2 K.H.B Extn Heggeri Colony

1st main 2nd cross old hubli

HUBLI: 580024

KARNATAKA

Mobile No: +918*********

Email ID: ********.*******@*****.***

Career Objective

To work with zeal for a Company that offers me a consistently positive atmosphere to learn

new

Technologies and implement them for the betterment of the organization.

Academic Profile

Examination Board Name of the institution Year of Percentage

passing

M-Tech Visvesvaraya PG Studies Of Visvesvaraya 2012-2014 74.14

(VLSI & Es) Technological Technological University,

University, Belgaum, Karnataka.

Belgaum,

Karnataka.

BE(E & C) Visvesvaraya Rural Engineering College 2008-2012 61.60

Technological Hulkoti

University,

Belgaum,

Karnataka.

Intermediate Department of Pre- RBP Rotary IND PU College 200*-****-**

University

Education,

Karnataka

Matriculate Karnataka Sri Revanasiddeshwar 2005-2006 69.60

Secondary Residentail High School

Education Siddaruda Nagara Old Hubli

Examination Board, Hubli

Technical skill:

Programming Languages: C, C++, Embedded C, Verilog, VHDL.

Simulation tools: Cadence, Mentor Graphics, LT Spice, Magic tool.Xilinx

Operating Systems: LINUX, Microsoft Windows XP, VISTA,

Workshop attained:

ASIC DESIGN USING OPEN SOURCE TOOL EDA(ALLIANCE)

CADENCE ANALOG DESIGN

HARNESSING TECHNOLOGY SKILLS FOR EMPLOYABILITY

Projects:

MTECH:

Design and Implementation of Sleepy Stack SRAM for reduction leakage power

The project was undertaken for power dissipation is one of the major concerns of very large

scale integration (VLSI) circuit’s design, for which CMOS is the primary technology. With

increasing chip densities, leakage power has become domain in memory design. To achieve

low power operation I have chosen Sleepy Stack SRAM cell to design 64 bit memory of

8wordsX 8bits.This work targets reduction of power dissipation in SRAM System during both

active and standby mode of operation. To reduce power dissipation high Vth devices are

incorporated appropriately. This cell also reduces dynamic power consumed during active

mode of operation compared to conventional 6T SRAM cell. This work addresses design,

simulation, and functionality verification of 8X8 memory array using sleepy Stack cell. The

layout is drawn and verified using 90nm GPDK process in cadence virtuoso tool. The access

time is also improved as compared

to 6T SRAM System with good data stability.

BE:

Vehicle theft control using android phone

Avoiding Vehicle Theft is making buzz in present automobile industry. Design and

development of a theft control system for an automobile, can be achieved by making use of

GPS feature of mobile phone. The developed system makes use of an mobile phone that is

embedded in the vehicle with an interfacing to Engine Control Module(ECM) through Control

Area Network (CAN) Bus, which is in turn, communicated to the ECM. The vehicle being

stolen can be stopped by using GPS feature of mobile phone and this information is used by

the owner of the vehicle for future processing. The owner sends the message to the mobile

which is embedded in the vehicle which has stolen which in turn controls the vehicles engine

by locking the working of the engine immediately. The developed system accept the message

and broadcasted to the Vehicle Network through CAN Bus. The engine can be unlocked only

by the owner of the vehicle by sending the message again. The goal behind the design is to

develop security for vehicles and embedded system to communicate with engine of the vehicle

Personal Details:

Father’s Name : Shivashankar.Dharani

Mother’s Name : Hemavathi.Dharani

Gender : Male

Date of Birth : 23rd January 1991

Languages Known : Kannada, English and Hindi

Hobbies &Interests: Volley ball, Cricket, Carom, Running, Chess.

The above given information is true to the best of my knowledge,

Place: HUBLI

Date:20/9/2014

Chanakya.Dharani

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