Engineer Project

Tejaswini Khobare

Phone: +91-974******* Email: ****.*******@*****.***

House No 503,Kuvempu Main Road, Hebbal Kempapura, Bangalore - 560 024

OBJECTIVE

To work in a stimulating and challenging milieu that would facilitate the

maximum utilization and application of my broad skills and expertise in

making a positive difference to the organization.

EDUCATION

M.Tech with specialization in VLSI & Embedded System Design from REVA

Institute of Technology & Management in 2013 with 72.50%

B.E with specialization in Electronics Engineering from Shivaji University,

in 2008 with 64%

COMPUTER SKILLS

Operating Systems: Windows XP/2000,Linux

Languages: C, Embedded C, Embedded System Knowledge, Verilog

HDL, Basic of System Verilog HVL.

Hardware: JTAG Interfacing, FPGA Spartan-3s.

Software: Keil uversion 2,3, Xilinx ISE Design Suite.

Simulator: ModelSim, Icarus Verilog, Cygwin, Verilogger Pro.

ACADEMIC PROJECT

> Design & Implementation of Programmable Logic Array Using Reversible

Logic.

In this project work, a proposed design of Reversible Programmable

Logic Array (RPLA) is constructing based on reversible logic gates.

The RPLA design is coded using Verilog Hardware Descriptive Language &

simulated on Xilinx 10.1 Design Suite. For design synthesis FPGA

Spartan-3s is used. The presented reversible PLA reduces the total

logical calculation & combinational path delay as compared to previous

work of RPLA.

. Platform / Software/ Tools: Verilog HDL language, Xilinx, FPGA

Spartan-3s

. Responsibilities: I have worked on each module of this project

along with decision making & time management.

WORK EXPERIENCE

1. VeriFxn PVT. LTD., Bangalore

Intern

Key deliverables:

At VeriFxn Pvt. Ltd., Bangalore (Sept 2013 -

March 2014)

. Learning & applying the basic concepts of Verilog & System Verilog

language.

. Daily follow up with senior engineer.

2. Medical Development & Engineering, Pune

Trainee Engineer

Key deliverables:

At Medical Development & Engineering, Pune (Feb 2009-Jan

2010)

. Responsible for development of Intelligent Tourniquet, Battery

chargers for Drill.

. Faults finding & rearranging new modifications in circuits at the

testing of Battery chargers.

. Testing of Battery chargers using battery packs used in Drill

instrument.

. Calibration & testing of Intelligent Tourniquets.

. Daily follow up with senior engineer.

3. Sun Pacific Enterprises, Pune

Trainee Engineer

Key deliverables:

At Sun Pacific Enterprises, Pune (Aug 2008-Feb

2009)

. Modification / Rectification of New Drawing.

. Copy to development design in any product.

. Instruments testing as Pulse transmitters, CNC drives etc.

. Daily follow up with senior engineer.

. Preparation of Project Report.

PUBLICATIONS

. M.Tech project work is selected in First International Conference on

Information & Communication Engineering (ICICE-2013).

TRAININGS

. Certified Embedded System Developer training completed from Prolific

Automation, Pune.

PERSONAL DETAILS

Date of Birth: 10th Jan, 1986

Marital Status: Married

Languages Known: English, Hindi and Marathi

References: Furnished upon request

(Tejaswini Khobare)

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