Pvt Ltd Training

CURRICULUM VITAE

NARESH MANDALAPU Email id: *****************@*****.***

Mobile No: +91-991*******

CAREER OBJECTIVE:

Aspiring a suitable position in a progressive organization that gives me an opportunity to

explore myself and contribute to the development of the organization.

ACADEMIC QUALIFICATIONS:

• Graduated in Electronic and Communication Engineering (2009-13) from Baba Institute of

Technology & Sciences(JNTUK), Visakhapatnam with an aggregate of 70%.

• Board of Intermediate Education (2007-09) from Sri Chaitanya Junior College, Eluru with an

aggregate of 93.8%.

• S.S.C (2006-07) from Z.P.H School, Vatluru with an aggregate of 87%.

VLSI DOMAIN SKILLS:

• HDL : Verilog.

• HVL : System Verilog .

• Verification Methodologies : CRT Coverage Driven Verification, Assertion Based Verification.

• Scripting Languages : Shell script (make), Perl.

• TB Methodology : UVM.

• EDA Tool : Modelsim, Questa and Xilinx ISE.

TRAINING EXPERIENCE:

• Certified VLSI Front End Verification Training in Maven Silicon Pvt Ltd, Bangalore.

VLSI PROJECTS:

GPIO IP Core - Verification using SV and UVM

Tools: Questa 10.0b.

Features verified:

• It is user-programmable general-purpose I/O controller.

• It provides toggling of general-purpose outputs and sampling of general-purpose inputs under software

control.

• Used to implement functions that are not implemented with the dedicated controllers in a system .

Router 1X3 – Design using Verilog HDL & Verification using SV and UVM

Tools: Xilinx ISE, Questa 10.0b,Verilog

Features verified:

• Packet routing

• Parity checking

• Sending packet, reading packet etc

Dual Port RAM – Design using Verilog HDL & Verification using SV

Tools: Xilinx ISE, Questa 10.0b,Verilog

Features verified:

• Implemented the Dual Port Ram using Verilog HDL independently.

• Architected the class based verification environment using system Verilog.

• Verified the RTL module using System Verilog.

• Generated functional and code coverage for the RTL verification sign-off.

Graduation Project

Joint Estimation Of I/Q Imbalance, CFO, Channel Response For MIMO OFDM Systems

Description:

Joint Estimation Of I/Q Imbalance, CFO, Channel Response For MIMO OFDM Systems

which estimates the in phase and quadrature phase imbalances along with carrier frequency offset, channel

response for multi input multi output ofdm systems.

ACHIEVEMENTS:

• I actively participated as "BUSY BEE" in BITSQUEST2013.

• I got a certificate for participation in IT WORKSHOP.

• I actively participated in NSS Camp held in our college.

PERSONAL TRAITS:

• Strong work commitment, Dedication and Determination.

• Quick learner.

• Able to Walk Extra Mile to Achieve Excellence.

PERSONAL PROFILE:

Name : M. Naresh

Father’s name : M. Nagendra Rao

Address : H:No: #1170, Thigalara Beedi,

Varthur,Bangalore-560087,

Karnataka(India).

Date of Birth : 15-06-1991

Languages known : English, Telugu.

Sex : Male

Marital status : Single

Nationality : Indian

DECLARATION:

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Bangalore.

(M.NARESH)

Contact this candidate