Design Engineer

Allada Veenanjali

Email id: ****************@*****.***

Mobile Number: +91-973**-*****

Career Objective:

Looking for a professionally satisfying and a challenging career in VLSI where the best of my abilities are used

for meeting professional as well as personal goals.

Core Competency:

Good understanding of fundamentals of CMOS Transistors.

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Good knowledge in IC Fabrication process & ASIC design flow.

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Hands on experience of block level physical design from RTL to GDS II.

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Hands on experience of layout design using icstudio by mentor graphics in 90 nm technology and

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performing DRC & LVS checks on it.

Hands on experience with industrial tools like Prime Time and IC Compiler.

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Good knowledge in pre & post layout Static Timing Analysis using Prime Time.

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Good knowledge on dealing with MCMM flow and OCV.

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Basic knowledge on DFT, scan chains and MBIST.

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Good working knowledge of Linux, C programming & TCL scripting.

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Good knowledge of Verilog RTL coding.

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Good knowledge of Digital Design Concepts.

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Implemented an embedded project during my under graduation.

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Education :

Institute Year of

Degree Discipline Aggregate

University Passing

PG Diploma VLSI RV-VLSI Design Center 2014

Sai Sudhir Institute of

Electronics & Engineering and

BE/B.Tech 2013 82.19 %

Communication Technology for Women

JNTUH

Narayana Junior College

12th MPC Board of Intermediate 2009 85 %

Education

Sri Krishnaveni Talent

10th 2007 85 %

School

Projects:

Physical Design and Verification SOC Subsystem

Title:

(TORPEDO).

Role: Physical Design Engineer.

Organization: RV-VLSI Design Center, Bangalore.

Duration of Project in Months: 6

Description: Technology : 180nm, Operating voltage : 1.8v,

Frequency : 400Mhz, Power Budget: 300mw, IR

drop : 5% ( VDD+VSS). This module is designed with

32 macros, 43000 standard cells, 6 metal layers. It is

operated with 5 clocks (3 propagated & 2 generated) &

the die size of 5.9 sq.mm

Steps involved: floor planning, power planning,

standard cell placement, CTS (Clock Tree Synthesis),

post CTS, routing, DFM (Design For Manufacturing)

and physical verification.

Tools Used : 1) IC compiler by Synopsys for physical design.

2) Prime time shell by Synopsys for Static Time

Analysis.

Deliverable/Challenges Faced: 1) Placement of macros with restricted orientations &

to avoid stacking of macros, managing congestion.

2) Understanding & coming up with solutions for

floating shape and floating pin errors.

3) Coming up with a good power plan with acceptable

amount of IR drop & minimum number of metal straps

by changing pitch and step size.

4) Analysing & fixing timing violations at every stage.

5) Identification of few violated paths among many

violating paths which need to be set as false paths.

6) Setting the optimization constraints to improve the

optimization of sub critical paths.

7) Fixing the timing violations of fixable paths through

useful skew.

8) Identification of path with maximum skew and

latency after Clock Tree Synthesis (CTS).

Achievements:

Participated in “windows app fest” conducted by Microsoft at Bangalore which is an 18 hour app

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development marathon and a Guinness world record.

Presented a technical paper on “BRAIN MACHINE INTERFACE” in SAI SUDHIR PG College &

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achieved second prize.

Presented a technical paper 0n “E-BOMB” at a national level meet held at SRINIDHI College.

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Personal Profile:

Name : Allada Veenanjali

Date of Birth : 11/Mar/1992

Address : #1456,17th C Main,HBR layout,5th Block,Kalyan Nagar post,Bangalore-43

Father Name : Jaya Rao

Nationality : Indian

Sex : Female

Languages known : English, Hindi, Telugu

Place : Bangalore

date : 6/06/2014

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