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Test Development Engineer

Location:
Cebu City, Central Visayas, Philippines
Posted:
April 24, 2014

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Resume:

Gerald Munar, M.S. [pic]

** ******* **., *** ********* Del Monte, Quezon City

Philippines 1105

Birthday: July 17, 1983

Sex: Male

Nationality: Filipino

Mobile Number: +639*********

LinkedIn /Email: acdur5@r.postjobfree.com

Qualifications

Eight years experience in semiconductor manufacturing industry in the field of

Test, Product and Process Engineering. Broad experience in developing test

solution, functionality and reliability testing, product yield improvement,

process improvement, product transition and new product releases. Demonstrated

capability to lead cross-functional teams in a multi-cultural environment. An

MS degree holder.

Technical Skills:

C/C++, NI Labview/Teststand, Cadence Schematic & PCB Design, VBScript, Perl,

Java, UNIX,

Advantest T2000, Teradyne uFlex, S9k Schlumberger, CTS LCT Mixed Signal

Tester, MCT Strip

Trained in Six Sigma, DOE, FMEA, SPC, 8D, JMP, SPSS Statistical Tool, STDF

Analysis

WORK experience

Test Development Engineer

January 2010 - Present

Analog Devices Inc.

Project Management - assumed PM role for Linear Precision Group. Chairs weekly

conference meeting with Product Line counterparts in the US for project

updates. Monitors more than 20 projects per quarter on average. Works with 7

peer engineers working with their respective projects and support them during

new product release stage. Coordinates with manufacturing and other

stakeholders with regards to the release requirements and other issues with

their products.

Test Development - Handles Level II test development projects for Op-Amps and

Voltage reference products. Develops test hardware (schematic/layout) and

program on different test platforms (single-form, strip-form), packages (SOIC,

TSOT, TSSOP, MSOP, LFCSP, SOT23), and temperatures (Ranges -55 to 175c).

Experienced developing solution for wafer probe level.

New Product Evaluations - Performs characterization, yield and CPK analysis,

correlation, guardband, repeatability, bench test, and EOS check. Performs

thorough engineering data analysis.

Offshore Subcon Release - Coordinates the transfer of test solution to

offshore test sites, approves site-to-site correlation result and monitor the

completion of first inventory lot.

Platform Migration - Handled test-platform migration project, and handler

migration project.

Product Qualifications - Develops test solution for Qualification and

Reliability testing. Assists in time-zero pre-Rel and post-Rel testing that

undergone temp cycle, HAST, ESD and other stress test for products being

qualified for Automotive industry.

Test Cost Reduction - Collaborates with Product Engineers to optimize test

yield, eliminate test pass, and test time reduction.

Product Engineer

July 2007 - July 2009

Intel Corporation

Product Sustaining - Responsible for the sustainability of product health

indicators including yield, test time, retest/recovery improvement and hold

lots disposition of below products:

IXP24xx Xscale ARM Network Processor (Castine), FCBGA

IXP28xx Xscale ARM Network Processor (Sausalito), FCBGA

ICH7 Mobile, ICH7 Desktop, ICH7R/DH Chipsets, BGA

Test Program Revisions - Revise test programs for test-hole reduction and

yield improvement. Performs Correlations, Code Review, Yield Review, and White

Paper Review.

Yield Improvement - Track Assembly, Test and Backend yield problems and

initiate appropriate experiment and solution for improvement. Collaborate with

multiple groups as necessary.

Customer Return Analysis - Analyzes customer-returned units by validating,

debugging, and track historical data. Improves Test program to prevent further

potential test-reject escapee. Performs FMEA, code review. Interfaces with FAB

& SORT sites in Ireland, Subcon Assembly in Malaysia, Design group in US, and

local groups for all product-related matters.

Business Travel: Engaged in Penang Site, Malaysia to work on a Product Site

Transfer, transitioning Network Processor Products from Philippines to

Malaysia. Trained Malaysian counterparts on Test Program sustainability, ATE

debug procedures and maintainability of core Product Health Indicators.

Provided consultation to Malaysian counterparts and trained FA engineers for

debug procedure using S9K Schlumberger Tester. Monitored the Site-to-Site

correlation and qualification activity until closure of transition.

Process Engineering Technician

June 2005 - July 2007

Intel Corporation

Manufacturing Process Monitoring - Sustained Test/Backend manufacturing

process of Kedron, Almagor M/R RF Integrated Transceivers for Intel

PRO/Wireless Adapters. Chipsets product includes ICH7, ICH8 and ICH9 and

Legacy Products including Almador (Pentium III-M mobile chipsets), and

Calistoga (Core/Core 2 mobile chipsets).

New Process Implementation - Engaged on New Products introduced for

High-Volume production. Develops new process and standard operating procedure.

Generate specifications for inspection criteria for new defect types.

Train/Certify operators on the new process.

Manufacturing Yield Improvement - Performs low yield analysis, visual defect

inspection thru high magnification and other inspection tools. Generate defect

Pareto and performs commonality analysis and other engineering data analysis

tools to establish potential root cause.

Sustaining and Quality Assurance - Attend hold lots and give appropriate

disposition. Initiates meeting with the responsible groups to address

questionable materials. Investigates quality and SOP violation issues,

document the problem and initiates resolution.

Process Cost Improvement - Eliminates redundant process and re-define a more

efficient and cost-effective process.

SELECTED ACCOMPLISHMENTS AND AWARDS RECEIVED

Recognized for fast implementation of new test solution for ADR431

guaranteeing better performance, resulting to new customer with potential of

60k vol/year or $304k/year (ADI 2010)

"Customer Advocacy Award" for the diligence in the customer-return validations

and debugs that resulted to an improved customer satisfaction (Intel 2008).

Led a task force with diverse team of engineers to address ICH7 SBL-Trigger

issue that resulted to a resolution and ~40% Hold-Lots Reduction (Intel 2008).

"Division Recognition Award" for the outstanding effort in releasing two high

quality test-programs that improves Bin1 Bin Split by 40% (Intel 2007).

Lead of the successfully implemented NSD Project that has US$16M ROI after 4

years by working with offshore teams and local groups (Intel 2006)

Technical Paper: Ball Inspection Elimination on FVI that reduces

over-rejection by 90% (2006).

EDUCATIONAL BACKGROUND

MS in Management Engineering

2006 - 2011

University of Santo Tomas - Graduate School

GPA of 1.31, equivalent to Cum Laude

Delegate of Joint Interschool Academic Program to Yokohama National

University, Japan (2009)

BS in Computer Engineering

2000 - 2005

Polytechnic University of the Philippines



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