Design Engineer
Resume:
Vishnu Vaishnav
Ariba PG '***',
Next to Reliance Mart,
Arekere Gate,
Bannerghatta Road, Email :
***********@*****.***
Bangalore-560076
Mo. +91-779*******
Career Objective
To work as a Verification/ Design Engineer in an organization where I can
utilize my technical skills for organizational development and my
professional career growth.
Summary of Qualifications
> Good understanding of the ASIC and FPGA design flow
> Hands-on Experience in writing RTL models in Verilog HDL and
Testbenches in SystemVerilog
> good knowledge in verification methodologies
> Hands-on Experience in using industry standard EDA tools for the front-
end design and verification
VLSI Domain Skills
HDL: Verilog
HVL: SystemVerilog
Verification Methodologies: Coverage Driven Verification
Assertion Based Verification
TB Methodology: UVM
EDA Tool: Questa sim and ISE
Domain: ASIC/FPGA Design Flow, Digital Design
methodologies
Knowledge: RTL Coding, RTL Verification
Code Coverage, Functional
Coverage, Synthesis,
Static Timing Analysis, ABV
Professional Qualification
Maven Silicon Certified Advanced VLSI Design and Verification course
from Maven Silicon VLSI Design and Training Center, Bangalore
Year: December 2013
Bachelor of Engineering, L.C.Institute of Technology,Bhandu,Mehsana.
Gujarat Technological University,
Gujarat, India
Discipline: Electronics and Communication Engineering
Percentage: 6.52
C.G.P.A with 1st class
Year: May 2013
H.S.C. (10+2) : New Meghdoot School
Secondary Education Board
Percentage : 60.80 %
Year :May 2009
S.S.C. (10) : Rashtrabharti Hindi Highschool
Gujarat Secondary Education Board
Percentage: 75.08%,distinction
Year :May 2007
Internship Experience
June 2012 _ April 2013, Vamendu Electronics,Gandhinagar,Gujarat
June 2013 - October 2013, Maven Silicon, VLSI Design and Training Center-
Bangalore
VLSI Projects
AMBA AHB-APB Bridge Design And Verification
HDL: Verilog
HVL: Verilog
EDA Tools: Xilinx ISE Design Suite, Questasim.
Description :
> Architected the design and described the functionality using Verilog
HDL.
> Verified the RTL model using Verilog.
SPI Master Core- RTL Verification using UVM
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools and Environment: Modelsim, Questa - Verification Platform
Description : SPI Master Core is a synchronous serial interface and it is
widely used to provide economical board-level interface between different
devices such as microcontrollers, DACs, ADCs and other.
.
> Architected the class based verification environment using UVM.
> Verified the RTL model using class based UVM TB..
> Generated functional and code coverage for the RTL verification sign-
off
Router 1x3 - RTL Verification using UVM
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools and Environment: Modelsim, Questa - Verification Platform
Description : The router accepts data packets on a single 8-bit port called
data and routes the packets to one of the three output channels, channel0,
channel1 and channel2.
.
> Architected the class based verification environment using UVM.
> Verified the RTL model using class based UVM TB..
> Generated functional and code coverage for the RTL verification sign-
off
RAM SOC - RTL Verification using UVM
HVL: System Verilog
TB Methodology: UVM
EDA Tools and Environment: Modelsim, Questa - Verification Platform
Description : The Design Under Test(DUT) fot this verification test bench
is RAM SOC.
It includes four instances of 4096 x 64 RAM chip
> Architected the class based verification environment using UVM
methodology.
> Verified the RTL module using the UVM class based TB.
> Generated functional and code coverage for the RTL verification sign-
off
Dual Port RAM - Verification using System Verilog
HVL: System Verilog
EDA Tools and Environment: Modelsim, Questa - Verification Platform
> Implemented the Dual Port Ram using Verilog HDL independently
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using System Verilog
> Generated functional and code coverage for the RTL verification sign-
off
Router 1x3 - RTL Design
HDL: Verilog
HVL: Verilog
EDA Tools: Xilinx ISE Design Suite, Questasim.
Description : The router accepts data packets on a single 8-bit port called
data and routes the packets to one of the three output channels, channel0,
channel1 and channel2.
> Architected the design and described the functionality using Verilog
HDL.
> Verified the RTL model using Verilog.
> Generated code coverage for the RTL verification sign-off
> Synthesized the design
SPI & I2C(IC) TESTING USING PIC MICROCONTROLLER
> It includes testing of SPI & I2C(IC) using PIC microcontroller.A
specific PIC-18f4520 is used in this tester.
Declaration
I hereby declare that the information given here with is correct to
best of my knowledge and I will responsible for any discrepancy.
Place :Bangalore Vishnu
Vaishnav
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