Engineer Project

Swapna Mutukulloju

Email: ******.***@*****.***

Phone: 965-***-****

Hyderabad 500-013

Career Objective

To be a part of the Microelectronics industry that provides me an

opportunity to exhibit and further develop my technical and analytical

skills through learning & research

Experience Summary

An Electronics Engineer with around 1.5 years of experience in front-end

digital logic design.

. FPGA design flow from RTL to netlist

. Experience on VHDL and Verilog

. Experience in real time debugging of Xilinx Chip scope Pro and Logic

Analyzer

. IP core Functional models of XILINX tool

. Knowledge of General Electric board(ICS-1555A)

. National Instruments (NI) Lab View.

. Knowledge of PCI-e bus

Technical Skills

. Verilog

. VHDL

. Xilinx Tool

. ModelSim

Experience

Micro Systems & Services, Hyderabad, India August 2012 to

December 2013

Junior FPGA Engineer

Client - Electronics System Engineering Center, DLRL, Kanchanbagh,

Hyderabad

Responsibilities:

. Create IP core containing the tests and coverage documentation from

the given specifications.

. Develop and create reusable test bench environments, reference and

coverage models, and assertions.

Achievements:

. Developed the FFT-16k

. Developed the ADC to FPGA interface

. Developed the tests and the assertions for the Wide band Signal

Processing

NEOSCHIP TECHNOLOGIES, Hyderabad, India July

2011 to June 2012

Trainee

Responsibilities:

. Understand the specification and develop the Micro architecture

document

. Design the project in verilog HDL

. Debug the code to Xilinx board.

. Synthesis and timing closure

Projectss:

. Design of ALU 16-bit

. LCD interface with FPGA

. Designed the UART Tx.

. Synthesis and deliverable with bug free rtl

Project Summary

> Processor Hardware for HF and V/UHF Search Receivers

The main aim of the Project is performing scanning, searching, detecting

and isolating signals of V/UHF Search receiver in the frequency range from

20MHz to 3000MHz.The HF Search receiver frequency range is 1.5-30 MHz. The

frequency ranges of IF section is 70MHz. The RF front end detects the

signal in the range of 20 MHz and performs scanning and provides an IF

section at a range of 70Mhz.The Data Acquisition module accepts an IF

signal and digitizes it and sends it to processor. The wideband signal

processing unit performs the processing of FPGA and control unit. The

obtained Processing is provided to operator work station. FPGA is used to

execute critical functions. The total development is of software defined

radio

Responsibilities:

. Generated Xilinx IP core for Wideband signal Processor and controller

unit individual module.

. Synthesized the modified RTL code on Xilinx Implementation tools

targeting to Xilinx Virtex 5 series XC5VSX95T.

. Tested all the modules of ICS-1555 hardware development code of GE.

. Integrated the wideband signal processing module with the ICS-1555

code.

Education

Course University Division Year

B.Tech Electronics & JNTU First Class 2011

Communications

Intermediate BIE Distinction 2007

SSC BSE Distinction 2005

References: Available on request

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