Pvt Ltd Power

Vinodh Cherukuri

*********@*****.*** +919*********

c/o Guravaiah Cherukuri, Bheemavaram (Vill), Poli (Post), Sri Kalahasti (Taluk), Chittoor (Dist.)-517620

Andhra Pradesh, india.

Objective

To secure a challenging position where I can effectively contribute my skills, and innovative ideas to gain

knowledge in the work oriented environment.

Education

2012-2014 M.Tech – MicroElectronics, Manipal Institute of Technology, Manipal (CGPA: 9.0)

2007-2011 B.Tech – ECE, Sri Indu College of Engineering and Technology, Hyderabad 77.9%

2005-2007 Intermediate, Narayana Junior College, Nellore 87.8%

2005 SSC, Mother Academy, Venkatagiri 85.0%

Skills

Languages Verilog, system Verilog, PSpice and RDL (Register description language) like RALgen and

Nebulon, assembly language (8085 & 8086 microprocessors).

Tools VCS, Xilinx - ISE and VIVADO (FPGA platform), Chip Scope Pro, CoreAssembler, MicroWind,

CADENCE Virtuoso and Collage.

Operating system Windows family, Unix.

• In-depth working knowledge of Cryptography systems, Symmetric-key and Public-key cryptosystems.

• Good working knowledge in RTL design, simulation and synthesis using Xilinx ISE, XST tools.

• Familiar with Xilinx virtex-7 and similar boards.

Awards/innovation

• Filed Innovation Disclosure Form (Brevetto ID: 110419).

• Secured 3rd rank in M.Tech first year at Manipal University.

• Secured 3rd rank in Board of secondary education exams at Mother Academy.

• Secured Organizational Award at Intel India for filing innovation disclosure.

• Submitted one Demo and one Poster presentation for Intel innovation day 2014.

Professional Experience

Intern, Intel Technology India Pvt Ltd. 2013-Till Date

Project:

Low Gate Count, Power Efficient and Fully Synthesizable Tiny Crypto Engine for Wearable SoC.

• A novel method to generate random numbers for encryption process of the data in crypto engine. The

solution is a low gate count, soft IP, fully synthesizable, easily portable to any process node/Emulation

platform.

• Different sets of entropy sources generated by Ring oscillator are injected in the Digital Random Number

Generator making it difficult to guess for an attacker and also resulting in an increase in the overall

Entropy of the system. It also provides very power efficient solution to the random number generation

problem.

• Light weight and ultra-low power serial AES hardware accelerators were used instead of large gate

counts. This design helped in reducing the area and power in SoC..

Advance SOC Integration

Better write about what u did for soc integration using collage than explaining what are capabilities of collage

• The idea is to integrate SOC platform to enhance design productivity based on IP reuse and IP-XACT

standard. Platform Integrator including CoreKit development to improve the efficiency and reliability in

platform integration, back end and Platform Verifier to improve verification time and work efficiency.

• In SoC Integration, the goal of Collage IP packaging is to minimize the number of ad-hoc signals

coming out of an IP by mapping ports to standard interfaces.

• Collage creates the right wrappers and punches ports through them. This enables quick changes in the

RTL hierarchy above the IP to handle back end/validation requirements and movement of IP from one

partition to another if needed.

Academic Projects

Universal Rotate Invert Bus Encoding For Low Power VLSI

• A technique for bus encoding which reduces the number of transitions on the bus and performs without

the need for extra overhead in computation and circuit. Irrespective of the bus width we needs three extra

bits to encode bus data and do not assume anything about the nature of the data on the bus.

Advanced Systems Laboratory (ASL), Ministry of Defense DRDO, Hyderabad

• A system that collects the input data in digital form with high accuracy and in short time which is then

processed by a microcomputer.

• Interconnection of a microcomputer to a data acquisition system to control a process involving several

input signals like temperature, pressure flow.

Active Filter Design Using Two OTA based Floating Inductance Simulator

• The circuit implementation is based on the use of OTA and Double output OTA (DO-OTA) as an active

element and a grounded capacitor. The resulting inductance can be electronically tuned by varying

external bias current accordingly.

• The feasibility of realization strategy is confirmed through SPICE simulations on Tanner EDA tool on

0.5μm technology.

DECLARATION

I hereby declare that the above-mentioned information is correct and I bear the responsibility for the correctness

of the above-mentioned particulars.

Vinodh Cherukuri

Contact this candidate