Design Engineer

ESHA DUBEY

**** ******** *****, #**** *** Jose, CA – 95134 *********@*****.*** 213-***-****

EDUCATION

University of Southern California, Los Angeles, CA Dec 2013

Masters of Science, Electrical Engineering - VLSI GPA: 3.2

Courses taken: Computer Architecture, VLSI System Design, Advanced VLSI System Design, Computer System Organization,

Analog Integrated Circuits and linear devices, Clean Room Fabrication and characterization of devices on a wafer

PESIT, Bangalore, India July 2010

Bachelors of Engineering, Electrical & Electronics GPA: 3.5

TECHNICAL SKILLS:

Tools : RTL coding using Verilog (Xilinx ISE, Modelsim), Design Compiler (Synthesis), Cadence tools ( Virtuoso,

Schematic, DRC- LVS,Formal Verification using Conformal, First Encounter – Place and Route, Primetime

for STA) :

Languages :System Verilog, Verilog, PERL Scripting, Basic C, Basic C++, Matlab / Simulink

WORK EXPERIENCE:

Graduate Technical Intern (KNL MIC Project – Intel, Santa Clara) June ’13 - Dec’13

LEC using Conformal for CPU subsystem

Flow setup for RTL2RTL fev

Apply the mapping process to debug unmapped key points, analyze and fix non-equivalencies and get past abort points

Implemented heirarichal fev run as compared to the flat run to get faster result.

Regression testing, work with design teams to debug failures and fix, and RTL sign -off on the design

Extensive use of PERL Scripting:

The nature of scripts was to automate the process of finding differences between 2 different RTL modules

Script for Post processing outputs of LEC using extensive pattern matching

Aug ’10 – Dec ‘11

Systems Engineer- Infosys, India

Developed and customized web-based portals on Microsoft SharePoint framework as part of a banking solution called ‘Finacle’

alongwith coding features in C, C++

ACADEMIC PROJECTS:

Spring ‘13

Multi-Core Processor Design using Network-on-Chip ( Verilog, Synthesis, STA, PnR)

Developed modules for network-on-chip & router and quad core processor with eventual integration using RTL Verilog

description and synthesis followed by verification using formal logical equivalency, static timing analysis and place & route

Synchronous digital SRAM Design – 1.00Kb (Cadence tools – Schematic, Virtuoso (DRC-LVS)) Fall ‘12

Designed schematic and custom layout of SRAM cell, pre-charge circuitry, sense-amplifier, write circuitry, row-decoder and

column-mux (design, timing analysis, power/area optimization)

Fall’ 12

Digital Image Uniform Noise Attenuation Project (Cadence Tools)

Implemented noise reduction in hardware in a team of 2 members using image processing, address generation unit and

control logic (pipelined mechanism),datapath unit and additional components like 1KB SRAM and 16 bit CLA

Fall’12

Clean Room Fabrication ( 3 inch wafer,class 100 clean room)

Fabricated mosfets,capacitors,diodes on a wafer and their characterization using photolithography

Summer’ 12

Pipelined Processor (Verilog, Modelsim)

Converted a single cycle CPU data path and control was to a 5-stage pipelined implementation and various additional units,

such as a Hazard Detection Unit and Flushing Unit.

Personal Traits:

Intel Recognition award winner for fast ramp up and contribution, team player, discipline d

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