VHDL, Verilog, System Verilog,OVM,UVM,TestBench and testcases devel

To exploit all aspect of my theoretical as well as practical knowledge

for the growth of my employer and my career at highest level. To work

efficiently and satisfactorily as a team member as well as in a

challenging and competitive environment to achieve expertise in the

allied fields through continuous learning in an organization of high

repute.

PROFILE:

. Clear understanding of object oriented programming concept and

System Verilog

. Experience in IP level and SOC Level Verification in System

Verilog

. Experience in Verification using methodologies such as UVM/OVM

. Verification using System Verilog Assertions and Coverage modules

. Experience in developing RTL in VHDL

. Worked on Generic Microcontroller based applications

. Experience in debugging VHDL and Verilog designs

. Excellent problem solving skills, good communication and

interpersonal skills

. Designation: Verification Engineer

SUMMARY:

. Verification Engineer in Silicon Partner Design Services Pvt Ltd.,

Bangalore since 9th July 2013

. Verification Engineer in RF Silicon Pvt Ltd, Noida from 30th May

2011 to 30th June 2013

PROFESSIONAL EDUCATION:

M.Tech(VLSI Design) from Banasthali Vidyapith University(Rajasthan)-

Overall Marks(77%)

B.Tech(Electronics and Instrumentation) from Sir Chhotu Ram Instiute of

Engineering and Technology(Meerut)- Overall Marks (85%)

TECHNICAL PROFICIENCIES:

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Operating Systems : LINUX (2.4.20-8), Windows 7/

2000/ XP

Area of Expertise : C, Verilog HDL, System Verilog,

VHDL, SystemC

Methodology : Open Verification

Methodology (OVM) and Universal Verification

Methodology (UVM)

EDA Tools & Kits : Mentor Graphics : Modelsim

Cadence :

NCSim

PROJECT DONE

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1) Project : UVM based Verification of FEBE(FrontEnd - BackEnd)

VIP

Role : Team Member

Details : FEBE VIP is a verification IP that has 3 modes :

FE mode (Used to send request transactions, BE mode (Used to send response transactions ), Checker

mode ( No virtual sequencer is there) . FEBE Model is made

independent of mode. It does operation for all 3 modes

depending upon the opcode it received in transaction. The

testbench environment instantiates 3 models . One for each

mode.

Tasks:

- Understand the Specification of FEBE VIP

- Developed the feature list, assertions, coverages

- Developed Pseudocode for the model

- Developed Model

- Developed sequence

Verification : UVM environment

Tool Used : Cadence NCSim.

2) Project : UVM based Verification of Wishbone Bus

Role : Individual

Details : Develop the driver, monitor and sequences using

UVM TestBench.

Tasks:

- Understand the Specification of Wishbone bus

- Developed Verification Plan

- Developed Testbench

- Developed testcases

- Written Functional coverage

Design : Verilog

Verification : UVM environment

Tool Used : Cadence NCSim.

3) Project : SHA IP Design and Verification.

Role : Team Member

Details : The cryptographic secure hash algorithms are

commonly used functions that takes an arbitrary

length input message and returns a unique

fixed length output value known as the message

digest. The digest is effectively a

compressed but irreversible representation of the entire input

message which can be used to provide data

integrity checking, since changes in the digest

indicate the message has also been changed.

Tasks:

- Understand the Design Specification of Secure HASH

Algorithms (SHA 256 / 224)

- Suggested various improvements in Design Specification

- Developed Verification Plan for SHA

- Developed Testbench For SHA

- Developed testcases and debugged the functional failures.

- Interface with designer on regular basis to discuss these

failures.

- Written Functional coverage

- Delivered the IP with all the functionalities tested

Design : Verilog

Verification : System Verilog (UVM environment)

Tool Used : ModelSim.

4) Project : MCU_IP Design and Verification.

Role : Team Member

Details : The GPIO module can be configured to be input or

output, enabled/disabled, input values are

debounced/ non debounced, input values can

be used as rising/falling/both/none edge

configurable interrupt source

Tasks:

- Understand the Design Specification of Generic General

Purpose Input/Output (GPIO) Port

of a microcontroller unit

- Suggested various improvements in Design Specification

- Developed RTL in VHDL

- Developed Verification Plan for Generic GPIO

- Developed Testbench For Generic GPIO

- Written Assertions, code coverage modules, functional

coverage modules and toggle coverage

modules to ensure 100% verification

- Developed Generic testcases and debugged the functional

failures.

- Interface with designer on regular basis to discuss these

failures.

- Delivered the IP with all the functionalities tested

Design : VHDL

Verification : System Verilog (OVM environment)

Tool Used : NCSim.

5) Project : Generic Interrupt Controller Design and

Verification.

Role : Team Member

Details : The IRQ controller handles independent interrupt

sources. Functions such as interrupt Pre- or

Post-masking, enabling and clearing are

available on different levels in the interrupt structure.

The number of interrupt sources is generic.

Each interrupt source having configurable priority.

Tasks:

- Understand the Design Specification of Generic Interrupt

Request(IRQ) Controller.

- Suggested various improvements in Design Specification

- Developed Verification Plan for Generic IRQ controller

- Developed Testbench For Generic IRQ controller

- Written Assertions, code coverage modules, functional

coverage modules and toggle coverage

modules to ensure 100% verification

- Developed Generic testcases and debugged the functional

failures.

- Interface with designer on regular basis to discuss these

failures.

- Delivered the IP with all the functionalities tested

Design : VHDL

Verification : System Verilog (OVM environment)

Tool Used : NCSim.

INTERESTS:

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. Solving puzzles and technical problems

PERSONAL DOSSIER

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Father's Name : Mr. J.P. Sharma

Languages known : English, Hindi

Date of Birth : 8th Dec, 1987

Marital Status : Single

Nationality : Indian

Passport Holder : Yes (Indian)

I hereby declare that all the above-mentioned information are given by

myself and are true to the best of my knowledge

Anamika Sharma

ANAMIKA SHARMA

Current address : #818/E, 17 Main, 6th block, Koramangala,

Bangalore(Karnataka) - 560095

Email: *******.******.**.**@*****.***,*******.*******@**********.***

Mobile No: 074******** / 078********

Contact this candidate