VLSI-design, Verification.

Gopal Lingappa Pujari.

Juhu Lane Dhangar wadi, near Laxmi- Email:

**********@*****.***

Temple Andheri(W), Mumbai-58, Mobile: +91-973*******

Maharastra, India

Personal Details:

Father's Name : Lingappa Hanumantha.

Mother's Name : Shivalingamma Lingappa

Occupation : Shopkeeper

Date of Birth : 8th August 1991

Nationality : Indian

Languages Known: English, Hindi, Kanada, Telugu & Marathi.

VLSI Domain Skills

HDLs: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification

TB Methodology: UVM, OVM

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design

methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional

Coverage, Synthesis,

Static Timing Analysis, ABV

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

Year: July 2013

Bachelor of Engineering, Finolex Acedemy of Management & Technology,

Ratnagiri. Mumbai University,

Maharastra, India

Discipline: Electronics & Communication

Engineering

Percentage: 62.33% First Class

Passing Year: July 2013

Intermediate(10+2) Cosmopolitian, Valia junior college, Mumbai, State

Board, Maharastra, India.

Discipline: H.S.C

Percentage: 79.5% First Class

Passing Year: March 2009

SSC(10th) S.R.W.S Welfare High School, Mumbai, State Board, Maharastra,

India.

Discipline: S.S.C

Percentage: 75.5% First Class

Passing Year: March 2007

Experience

. August 2013 - January 2013, Maven Silicon, VLSI Design and Training

Center

VLSI Projects

SPI Controller Core - Verification

> Architected the class based verification environment using system

Verilog

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

Router 1x3 - RTL design and Verification

Description:

The router accepts data packets on a single 8-bit port called data and

routes the packets to one of the three output channels, channel0, channel1

and channel2.

> Architected the design and described the functionality using Verilog

HDL.

> Architected the class based verification environment using system

Verilog

> Verified the RTL model using SystemVerilog.

> Generated functional and code coverage for the RTL verification sign-

off

> Synthesized the design

Dual Port RAM - verification

> Implemented the Dual Port Ram using Verilog HDL independently

> Architected the class based verification environment using system

Verilog

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

Engineering Project

Final Year Project : Interactive Voice Response System

Third Year mini project : Multivibrator using transistor,

Duty cycle generator using Decade counter &

Logic Level Detector.

DECLARATION

I hereby declare that the above information and particulars are true and

correct to the best of my personal knowledge and belief.

Date:

Place:

(P.Gopal.Lingappa)

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