Project High School

CURRICULUM VITAE

S.ANJI,

C/O:Srinadha Reddy building,

Room no:27, 2nd floor,

Vinayaka nagar,

Gollahalli main road,

Hebbagodi,

Email: *********@*****.***

Bangalore. (Phone:991-***-****

XCareer Objective:

To work in a challenging environment and where my personal skills and

knowledge are utilized for the growth of the organization. To learn day-to-

day experience in work and train myself to become the best in my area of

expertise.

&Educational Qualifications:

Course Board/University Percentage Year of

Passing

M.E R.M.K.Engg college,

(VLSI DESIGN) Chennai.(Anna uni) 73.20% 2013

MRRITS, Udayagiri,

B.Tech(ECE) A.P 61.44% 2011

12th (M.P.C) Govt. Junior

College, 79.00% 2007

Nandavanam, A.P

10th Z.P.High School,

Kavetigaripalli,A.P 61.00% 2005

:Technical Skills:

Area of interest : Digital Electronics

: Testing of VLSI Circuits

SKILLS & CERTIFICATIONS:

. Basics of C,C++ programming

. VHDL, Verilog and System verilog

. Matlab - Simulink

. Transistor level design- Virtuoso

. RTL to GDS Flow -IC Station, SOC Encounter

. Netlistdesign tool -DesignVision

. Functional verification-ModelSim,QuestaSim, NC Launch

. Synthesis tools - Quartus II, Xilinx ISE

?Achievements:

. I have participated in FDP on RMK ENGG COLLEGE.

. I have participated in workshops on Xilinx.

. An active good leader and Spl in school days.

. I got 2nd prize in zonal level at G.K.1

. I got 3rd prize in zonal level at Essay writing.

?Interpersonal Skills:

. Hard Working

. Confident

. Good communication skills

. Team facilitator

) Academic Project:

Project Title : "Design and Characterization of Parallel Prefix

Adders".

Project Description: The binary adder is the critical element in most

digital circuit designs including DSP and microprocessor data path units.

In VLSI implementations, parallel-prefix adders are known to have the best

performance.

Parallel-prefix adders also known as carry-tree adders. This

project investigates THREE types of carry tree adders (the kogge-stone,

sparse kogge-stone and spanning tree adder) and compare them to the Ripple

carry adder (RCA) and Carry skip adder (CSA).

There are designs of varied Bit-width were implemented on a Xilinx

Spartan 3E FPGA and delay measured. The RCA design exhibit better delay

performance up to 128 bits. The carry tree adders are expected to have a

speed advantage over the RCA as bit widths approach 256.

In this project (Verilog coding) for simulation we are use

MODELSIM for logical verification and further synthesizing it on XILINX-ISE

Tool.

?Declaration:

I here by declare that all the information

furnished above is true to the best of my knowledge and

belief.

Place : Bangalore (S.ANJI)

Date :

Contact this candidate