Engineer Electrical

David Y. Kao

***** ********** ****, ******, ** 750**-***-*** 4791 *********@*****.***

Objective Electrical Engineer on IC Circuit Characterization and Simulation

Experience Memory/EDA Engineer (6/2011 – 8/2013 Maxim Integrated, Dallas Texas)

Embedded Memory develop and characterizations for ROM, Dual-Port and Single Port SRAM.

Memory Instances characterization for Liberty (.lib) model generation.

SRAM Bit cell characterization (SNM Monte Carlo) and instance Function Verification (AMS/irun).

Advanced On-Chip Verification (AOCV) model generation and verification using Monte Carlo.

Staff Engineer (9/2008 – 5/2011 QUIPS, Austin Texas)

Memory related patent evaluation: circuit design and technology for SRAM, DRAM and FLASH

(MLC).

Memory architecture and data path analysis: I/O serializer/De-serializer; ODT/OCD combo, etc.

Image Sensor Array structure analysis.

Circuit Designer (7/2006 - 9/1008 Texas Instruments, Dallas, Texas)

Embedded SRAM memory Compiler: characterization using HSpice.

EMIR flow development: Synopsys/Prime Rail.

Formal verification for embedded SRAM: ESP-CV.

Base standard analog IP designer (2003-2006 Micron Technology, Boise, Idaho)

Power-up controller (Supply Voltage Supervisor): level detector and delay circuitry.

ODT (On-die-termination) for DDR2 SDRAM: Rtt and Vm trim structure and its driver design. The

circuitry is calibrated using HSpice parasitic devices extracted by Star/RC.

Internal Voltage reference: Half Vdd reference for cell plate reference.

Level shifter: High voltage with low degradation circuit design and characterization.

Senior CAD engineer (1996-2003 Micron Technology, Boise, Idaho)

Star-RC extraction flow and tools: technology file creation and testing.

Hercules/LVS flow and tools: debug interface and analysis tools.

Device extraction flow and tools: Hercules rule generator and option control.

Device and Modeling Engineer (1992-1996 Micron Technology, Boise, Idaho)

Spice model generation: BSIM model extraction and model generation, test structure design.

CMOS device parameter extraction methodology and test structures.

CMOS device structure optimization.

Education University of Maryland, College Park, Maryland (1989-1991)

MS of Electrical Engineering (Major: Microelectronics)

Tsinghua University, Beijing (1983-1988)

BS of Electrical Engineering (Major: Microelectronics)

Design tool EDA tools used

• Design Entry: Cadence virtuoso

Skills

• Simulation: Hspice, Spectre, Ultrasim, Finesim, SmartSpice, AMS, ncverilog

• Script: C, Perl, Skill, Perl/Tk, C-shell

• Formal Verification: ESP-CV (Synopsys), NC Verilog

• LVS/DRC: Hercules, Calibre

David Kao

12836 Cordellera Lane, Frisco, TX 750**-***-*** 2248 *********@*****.***

David Y. Kao

12836 Cordellera Lane, Frisco, TX 750**-***-*** 4791 *********@*****.***

Innovation 50 US Patents Issued

David Kao

12836 Cordellera Lane, Frisco, TX 750**-***-*** 2248 *********@*****.***

David Kao

12836 Cordellera Lane, Frisco, TX 750**-***-*** 2248 *********@*****.***

Contact this candidate