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Project Engineering

Location:
Hyderabad, Telangana, India
Salary:
15 per month
Posted:
March 11, 2019

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Resume:

Valisetti Prashanth

Profile Summary:

* ***** ** **** ********** in Standard cell designs and Analog layouts.

Worked on TSMC 130nm and UMC 28nm

Worked on logic cells, layout placement, routing and verification checks.

Knowledge on WPE, STI, LOD, Multiple Patterning and failure mechanisms such as Antenna and latch up.

Good knowledge on physical verification checks DRC, LVS.

Good understanding on Bit cell structure.

Education Qualifications:

Bachelor of Technology in Electronics and Communication engineering from Sunflower College of Engineering and Technology, JNTU Kakinada

Tools / Skill set:

Layout Tools : Cadence, Virtuoso-L,Virtuoso-XL.

Verification Tools : Assura & PVS

Operating Systems : Linux, Windows.

Professional Experience:

Ferventz Semiconductor Hyderabad - Telegana

Custom Layout Trainee

Project:

Title : Standard cells development

Technology : TSMC 130nm

Tools : Virtuoso-L, Assura & PVS.

Role-played:

Designed layout for standard cells like INV, AND, OR, NOR and NAND cells.

Designed the standard cells with 11 track height.

Followed half DRC methodologies for all the standard cells.

Project:

Title : TEMPERATURE SENSOR Analog layout development

Technology : UMC 28nm

Tools : Virtuoso-XL, PVS.

Role-played:

Designed Common Centroid matching technique for Differential pairs and ID matching for current mirrors.

Followed DRC methodologies and LVS.

Layout of CMOS Inverter and Logic Gates like AND, OR, NOT.

Project 2

Title :TRANSMITTER

Technology : UMC 28nm

Tools : Virtuoso-XL, PVS.

Role-played:

Customised layouts for modules present in the transmitter like logic gates INV, NOR and NAND cells, ZAP circuit, 3 state Buffer, Basic Cell, Tied Circuit, Decoder, Multiplexer.

Designed the custom cells with 11 metal track height.

Followed half DRC methodologies for all the standard cells

Project 3:

Title : Vref Buffer

Technology : UMC 28nm

Tools : Virtuoso-XL, PVS.

Role-played:

Layout Design for the fully differential voltage reference modules

Completed DRC& LVS for all the layouts

Project 4 :

Title : Ring oscillator

Technology : UMC 28nm

Tools : Virtuoso-XL, PVS.

Role-played:

Customised layouts for modules present in the differential symmetry like level symmetry Designed.

Completed DRC& LVS for all the layouts.

Project 5 :

Title : Band gap

Technology : UMC 28nm

Tools : Virtuoso-XL, PVS.

Role-played:

Worked on Error Amplifier, BJT matching and resistor matching

Completed DRC& LVS

Project 6:

Title : Low Noise Amplifier(LNA)

Technology : UMC 28nm

Tools : Virtuoso-XL, PVS.

Role-played:

Inductor Isolation technique.

Routing of high speed lines

Matching od devices.

Followed DRC& LVS methodologies for all the layouts

Personal Profile:

Languages known : English, Telugu,

Nationality : Indian

Current Location : Hyderabad



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