Sign in

Computer Engineering

Redwood City, California, United States
September 07, 2018

Contact this candidate



Clemson University

M.S. Computer Engineering 2018

GPA : 3.5


University of Pune

B.E. Electronics and Telecommunication 2016

GPA : 3.75

xv6 Kernel Modifications(Unix/Linux/C) Spring 2018

Added new functionalities to xv6 kernel which is a simple re-implementation of Unix Version 6. The new features include :

Null pointer dereference to invoke a trap to prevent the access of code section of the process. Processes communication through shared memory pages.

Multi-threading support using spin lock for synchronization.

Priority based simple Multi-level Feedback Queue scheduler with robin-round for tie breaker.

File system checker to check the consistency of file system image and implementing File system integrity to add protection from data corruption.

FPGA Acceleration for K-means clustering algorithm(Altera/OpenCL/C++) Spring 2018

Implemented efficient k means clustering algorithm on Altera Stratix V FPGA, to exploit the inherent parallelism along with the use of pipe-lining and Altera specific channels.

Embedded Computing for multimedia processing.(Linux/C) Spring 2017 Implemented a kernel driver in C on Linux that provides sound playback capabilities where it uses DMA for writing into the device registers of the sound blaster audio card.

Implemented RLE, LZW, Huffman codecs to run them successfully on images, text files and binary executable files.

Implemented image rendering from PLY file in C to display the images in ppm format with different camera orientations provided by the user.

RMA Scheduling for RTOS(Linux/C) Spring 2017

Implemented scheduling for RTOS using Rate Monotonic Analysis for simulation of Intertial Navigation System,a real-time shipboard avionic system running on Motorola MC68302 microcontroller and linux real-time kernel.

Nonlinear Tracking and Non-Gaussian Filtering using Particle Filter Fall 2017 Developed a nonlinear system model for indoor tracking using a filter with 1000 particles using Monte-Carlo Approximation.

Prior Importance Sampling was employed for weight approximation and re-sampling.

Optimum performance achieved through trade-off between re-sampling frequency and number of particles.

Parallel Programming( MPI/C) Fall 2016

Design, Implementation and Performance evaluation for Parallel implementation of Gaussian Elimination (checker board decomposition, partial pivoting and pipelined communication) .

Design, Implementation and Performance evaluation for Parallel implementation of Floyd’s all pair shortest-path using.

Developing virtual firewall based on Network Function Virtualization(C++) Spring 2017 Created micro middle-boxes to support basic ACL rules (stateless firewall features) for ICMP, UDP, TCP traffic on ClickOS based on Xen Hypervisor.

Traffic monitored via Open vSwitch for load balancing and traffic shaping.


Advanced Operating Systems, FPGA Design and Applications, GPGPU, Advanced Data Structures, Parallel Programming, Embedded Computing, Micro-controller and Applications, Analysis of Tracking Systems, Computer Network Security, Automotive Electronics, Artificial Neural Networks, Digital Signal Processing


Embionics Technologies Pvt Ltd Pune, India

Intern Summer 2017

Developing, testing and debugging firmware for IoT Protocol Stack.

Responsible for designing and programming data encryption and authentication schemes for MQTT protocol using ARM Cortex M0(Freedom KL25Z).

Indian Railways Institute of Civil Engineering India

Embedded Systems Intern Fall 2015 to Spring 2016

Smart railway track monitoring system(ARM/AVR/C)

Board bring-up to connect accelerometer, piezo- electric sensor based network with GPS, GSM and SD card modules, an efficient and low cost solution for automated monitoring.

In depth exposure to low-level communication protocols SPI, UART, device drivers.

Contact this candidate