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Verilog Coding,PCB layout and Circuit designing Etc..

Location:
Belgaum, Karnataka, India
Salary:
3.2 to 4 Lack PA
Posted:
August 28, 2018

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Resume:

RESUME

SAPANA ADHALLI Plot No ***, CTS No ****, Bauxite

ac6t9z@r.postjobfree.com Road, Hanuman Nagar, Belagavi,

Contact: +917********* Karnataka-590001.

Career Objective:

To excel in my area of activity, by taking up challenging assignments at the workplace, sharpen my skill by maintaining a learning attitude and contribute to the growth of the organization by harnessing these skills there by achieve my personal career objectives.

Technical Skills:

Good knowledge of transistors and circuit theory.

Good knowledge of logic design concepts.

Good knowledge of ASIC flow and FPGA flow.

Good knowledge of PCB manufacturing.

Good working knowledge of Verilog coding.

Good working knowledge of Xilinx, NC Simulator (Cadence) and Virtuoso (Cadence).

Good working knowledge of PCB and Circuit Designing in ORCAD (Cadence).

Good working knowledge of Electronic Circuit Designating and Simulation Software – SEQUEL.

Good working knowledge of MATLAB

Other Software’s – Microprocessor Software – MASM, Microcontroller Software – Keil

Programming Language – C,C++

Education:

Degree

Discipline

Institute/

University

Year of Passing

Aggregate

PG

VLSI and Embedded Systems

Dr. Ambedkar Institute Of Technology(VTU)

2016

75.41%

BE

Electronics and Communication

SCT Institute of Technology (VTU)

2012

68 %

PUC

II Year

R.L.P.U College of Science Belgaum.

2008

66 %

SSLC

State

Sherman Kannada medium high school, Belgaum

Karnataka Secondary Education Examination Board

2006

69.60 %

Professional Experience:

Company: Cycloid System Private Limited.

Designation: Application Engineer.

Duration: 1 Year (21 August 2012- 31 August 2013).

Worked on: PCB and Circuit Designing in Cadence OrCAD.

Job role involved following responsibilities.

Circuit and PCB designing in Cadence OrCAD.

Creating library for Circuit and PCB Designing Components.

Creating Gerber Files.

Arduino Programming to Embed the Designed boards.

M.Tech Academic Projects:

Title:

Design and Implementation of HRV and EEG Signal Analysis on FPGA

Organization:

Certitude technologies Pvt. Ltd.

Duration of Project in Months:

6

Description:

By means of analysis of HRV and EEG signal of Heartfulness Meditator and Non-Meditator observed the effect of Heartfulness Meditation in the health improvement.

Tools Used :

Xilinx 14.7, Spartan 3, Spartan 6 FPGA with Chipscope, MATLAB, Bio Pack system

M.Tech Academic Internship:

Mini project Title:

FPGA based modified router for NOC.

Organization:

Certitude technologies Pvt. Ltd.

Duration of Project in Months:

6

Description:

The different channels for the router are coded using Verilog and integrated to make a router for NOC.

Other designs:

Basic program relearning, Designing of Carry Save Adder, Modified Booth Multiplier in verilog.

Tools Used :

Xilinx 14.7, Spartan 3, Spartan 6 FPGA with Chip scope.

B.E Academic Projects:

Title:

Machine to Machine Interaction for failure prediction system

Duration of Project in Months:

6

Description:

Using Microcontroller Embedded System and Sensors. It is mainly used for automatic failure prediction and control of machines. And using GSM messages will be sent to plant operator mobile phone.

Tools Used :

Keil

Presentations and Papers Published:

Date: May 2018

Topic: “Science & U”

Presented: Thomson Reuters, Bengaluru.

Date: October 2016.

Authors: Sapana Adhalli, Dr. Rajeshwari Hegde, Dr. Mohandas Hegde.

Title: “Investigations on the effect of Heartfulness meditation on HRV and delta waves” Presented: Paramhansa Yogananda International Conference on Spirituality in Science, Education and Fine Arts

Date: May 2016

Authors: Sapana M Adhalli, H Umadevi, Guruprasad S P and Rajeshwari Hegde.

Title: “Design and Simulation of EEG Signals Analysis-A Case study”

Published: International journal of Engineering Science and Computing Volume 6 Issue 5, pp 6179-6187

ISSN No: 23213361

DOI 10.4010/2016.1494

Date: May 2016

Authors: Sapana M Adhalli, H Umadevi, Guruprasad S P and Rajeshwari Hegde.

Title: “Design and Implementation of EEG Signals Analysis on FPGA”

Published: International journal of Engineering and Computer science Volume 5 Issue 5, pp 166**-*****

ISSN No: 23197242

DOI: 10.18535/ijecs/v5i5.54

Key Achievements:

TEQIP Scholar Student in M.Tech during year 2014-2016.

Vice president in IETE Students’ Forum for academic year 2011-2012.

Control System Subject topper in college.

State level hockey player.

Camps star winner in Radio Mirchi.

Winner in circuit design computation held in college by Texas instruments.

Winner in school science exhibition.

Winner in district level Seed Art on World Environment day.

Won the second prize in PU inter-college singing competition.

Runner in intra-college athlete (Running) competition.

Hobbies:

Heartfulness Meditation

Writing inspiring thoughts

Singing

Drawing

Reading books

Personal Profile:

Name : SAPANA.M.ADHALLI

Date of Birth : 21st September, 1990

Father Name : Late. Muragesh R Adhalli

Mother Name : Ratna M Adhalli

Address : Plot No 258, CTS No 5054, RS No 183, Bauxite Road,

Hanuman Nagar, Belagavi – 590001

Mobile : +91-779*-**-**-**/ 861-***-****

Marital Status : Single

Nationality : Indian

Gender : Female

Languages known : English, Kannada, Hindi and Telugu.

Declaration:

I hereby declare that the above mentioned facts and figures are true to the best of my knowledge.

Date:

Place: Bengaluru (Sapana M Adhalli)



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