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Engineer Design

Location:
Seoul, Seoul, South Korea
Posted:
August 26, 2018

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Resume:

KHITISH CHANDRA BEHERA

Address: ****-**, *******, ************-**,

Yeongtong-gu,

Suwon-si, Gyeonggi-do

Republic of Korea

Mobile: +82-10-660*****

E-mail: ac6s9o@r.postjobfree.com

STAFF ENGINEER-II, MODEM LAB, NETWORK DIVISION, SAMSUNG ELECTRONICS, SUWON, SOUTH KOREA

Specialist in designing architecture and implementation of signal processing algorithms. Presently working on 5G NR Modem (for gNB) signal processing architecture and design implementation. Having 12 years of experience in high performance ASIC development. Having a strong understanding of all phases of front development including data path and control path architecture and design, RTL development, verification, timing closure and silicon validation. Driven by strong imagination, cherish in identifying the problem and solving, aspiring to take up leadership roles in the next career phase.

EXPERIENCE SUMMARY

• Presently working on 5G NR(Release 15) 6Ghz hardware Modem PUCCH channel Architecture, Design and Implementation and Verification.

• Have implemented 5G NR F234 PUCCH signal chain modules from scratch based on the fixed-point design.

• Presently verifying the signal chain with dedicated scenario Test Vectors from Algorithm Bit Design.

• System time budgeting across CE, FDEQ, DMAP, LDEC and RMAP for SIC for max-UE 8-layer MU-MIMO.

• Fixed point design study PUSCH receiver modules: Channel Estimation, MMSE-based FDEQ (Frequency Domain Equalizer).

• System architecture for LDPC for max system Throughput and Latency for max-UE 8-layer MU-MIMO.

• System SoC simulation for Frequency domain equalizer on PUSCH channel.

• Developed micro-architecture for RoE-SRIO interface bridge in Xilinx Ultrascale FPGA having 100G(10Lanex10Gbps) Ethernet (IEEE 802.3-2012) MAC and (4Lanex5Gbps) SRIO RapidIO Gen4 endpoint.

• Developed low-latency CA-SCL Decoding and SCD Decoding Algorithm for 5G Polar Codes in Matlab.

• Developed 5G LDPC Encoding and Decoding Algorithms in Matlab.

• Designed Matrix Inversion (configurable up to 32-layers and 128 Antennas) Hardware Accelerator for FDMIMO Detection.

• Polar Decoder algorithm and decoder micro-architectures to meet throughput requirements (> 10Gbps) for 5G.

• Designed LDPC decoder core to meet 10Gbps throughput for 5G.

• Proposed schemes such as data forwarding pipeline to remove idle cycles and gain throughput by 15% in layered decoding.

• Worked on performance analysis of 802.16e LDPC decoding in Matlab.

• Worked on Turbo Decoder architecture enhancements.

• Have done an in-depth study of LTE (Rel 13) specifications.

• Worked on system modelling of multi-lane pipelined index-scaled 2K FFT for 4G MODEM RX bit processing design in Matlab.

• Designed an ultra-low power STANDBY feature for MediaTek (Helio 4G Series) smartphone 20nm SoC product line, validated the design feature on Silicon validation activities.

• Worked on design fixes for PoR sequence for MediaTek smartphone SoC, validated the design on post-Silicon bring-up.

• Designed the ARM-CORTEXM4F based processor sub-system for 45nm SoC for TI’s 3G/LTE macro-cell base-station chipset solutions.

• Designed the AHBlite based interconnect fabric supporting programmable, fixed and round-robin arbitration schemes.

• Designed the arbitration architecture to meet the latency requirements from different masters on the BUS fabric.

• Designed the SEC/DED handling ECC capable memory sub system architecture.

• Defined the system architecture for the HART compliant CPFSK modem and designed the receiver signal chain of the modem.

• Defined the system architecture for a Secured Display system for financial transaction terminals.

• Designed 4096x4096 pixels (max), 24-bit Colour LCD controller driving all types of TFT/STN panel timing.

• Designed an Asynchronous State Machine for power sequencer applications in digital custom circuit in 65nm CMOS technology.

• Developed the block level and chip level constraints for pre-synth, pre-CTS, post-CTS and Post-Route functional mode

STA runs, analysed and identified timing fixes, handled full chip CDC for multiple ASIC product lines.

PROFESSIONAL EXPERIENCE

SAMSUNG ELECTRONICS, MODEM LAB, NETWORKS DIVISION,

SUWON, SOUTH KOREA

STAFF ENGINEER-II JANUARY, 2017 - PRESENT

5G NR (>6Ghz, 3GPP Rel. 15) F234 PUCCH (MLD and Coherent Mode) fixed -point receiver (for Base Station) modules Implementation from scratch: From Algorithm Bit Design to RTL implementation, UVM Based Verification and sub-chip level synthesis. Architecture Design and RTL implementation was done from scratch for the following modules:

RM Decoder IP Design, the major design challenges

• 3-stage butterfly, 3-clock latency FHT correlator design.

• FHT Correlator based hardware resource for RM and simplex design.

• 32-Sequence multiplier for rate-matched blocks, 2K accumulation logic.

• Candidate restriction logic, Erasure decoding, ML metric sorting logic.

DeRateMatching Module for RM and Simplex Decoder (N=32 for RMDecoder, N=1,2,3/6 for Simplex)

• Zero-padding at head and tail at HOP boundary if encoded bit count is not modulo-32.

Re-Demapping for CSI-part1 and CSI-part2.

16-sub-band RI extraction module based on 1st decoding of CSI-part1 decoding

CSI Part 1 & 2 Parser logic, NUM_Bits2 Calculation logic for CSI-Part2.

Multi-Slot combining Buffer flow control and management logic.

DeScrambler and PlaceHold Module for CSI-Part1 and Part2.

Multi-UE Buffer control Logic,

Re-ordering Logic for UE-by-CSI-part-by-HOP-by-symbol-by-antenna-by-tone.

Antenna combining, Hop Combining, Zero-Padding.

Low-Latency architecture to find MOD (to be published).

Code Buffer scheduler and arbiter Design supporting Code block segmentation and concatenation.

AXI4 slave interface design to do flow control with Decoder IP.

Erasure decoding to calculate the average for Polar Codes in PUCCH

• Unsigned Divider to calculate the PM averaging.

Multi-UE CPU parameter configuration module.

Whitenning Module Design

1. Designed from scratch the Matrix-Inversion Hardware accelerator IP micro-architecture, configurable up to 32-layers and 128 antennas for ZF and MMSE blocks.

Fixed-point design having configurable (in powers of 2) no. of multipliers.

Fixed-point sub modules include Cholesky-decomposition, Forward-Backward and inverse SQRT.

Block Level verification with reference-C in UVM.

5-stage pipeline data-path design. Fixed point implementation in Verilog. Block-level synthesis, constraints and STA (pre-synth, post-CTS) done at 1Ghz on 14nm technology.

Radio-Over-Ethernet – SRIO Bridge (on Xilinx UltraScale FPGA)

1. Developed architecture specifications for Radio-over-Ethernet-SRIO interface conversion logic on Xilinx Ultrascale FPGA having 100G Ethernet (IEEE E 802.3-2012) MAC (10Lx10Gbps) and SRIO Gen4 (4Lx5Gbps).

2. Designed the Packet Buffer management logic having 512-bit at 322.2Mhz on LBUS from EMAC and 64-bit at 250Mhz from Rapid IO, for Xilinx Ultrascale architecture in Verilog.

NR CODEC (LDPC, Polar Codes) Algorithm Design and Research:

1. Polar Codes

Extensive research and survey of low-latency CA-SCL Polar Decoder algorithms for 3GPP standard proposals.

Developed the CA Polar codes and PC polar code algorithms in Matlab.

Proposed a novel SCD Decoding architecture with decoding latency on the order of log2(N) cycles, N being the code length. It has been filed for patent.

Research Study on Polar Decoder algorithms for DSP implementation to meet 10Gbps throughput.

2. NR LDPC Codes

Developed layered decoding algorithms for NR LDPC BG1 and BG2 graphs in Matlab, proposed an enhanced scaled-min sum to achieve coding gain up to 0.35dB.

Developed efficient LDPC encoding architecture for implementation on DSP.

System S/W Development:

1. Commercialized LTE PHY L1 S/W development features for PUSCH channel.

a. SU-MIMO TM2 4-layer spatial multiplexing.

2. System time budgeting across FDEQ, DMAP, LDEC and RMAP for SIC for for max-UE 8-layer MU-MIMO.

3. PUSCH job chaining across FDEQ, TDEC, VDEC and UCI (ACK, RI, Periodic/A-periodic CQI) decoding for SoC system simulation.

MEDIATEK INDIA DESIGN CENTER, BANGALORE

SENIOR STAFF ENGINEER JANUARY, 2015 – JANUARY, 2017

NR Polar Decoder Design

1. Research Study on Low-Latency Polar Decoder algorithms for moderate length code block lengths.

2. Successive Cancellation (upto List size=16) Based Polar Decoder IP with bio-tonic sorter design operating at 800Mhz.

3.

802.11n LDPC Design optimization

1. Worked on LDPC decoder design changes to remove idle cycles and gain in throughput (by 15%) in layered decoding,

target throughput being 10Gbps.

2. Worked on FPGA synthesis, timing of LDPC design, proposed a scalable architecture to meet 10Gbps throughput on FPGA.

3. Worked on Turbo Decoder architecture explorations, proposed a radix-4 cascade decoding scheme to improve throughput.

4. Worked on performance analysis of 802.16e LDPC decoding algorithms in Matlab for 6-code rates and 18-expansion factors.

2K point SDF FFT Design

1. Worked on the hardware architecture modelling of multi-lane pipelined FFT in Matlab, the architecture employs index-scaling feature.

MediaTek SmartPhone SoC IP Design and Optimizations

1. Architected and implemented an ultra-low power STANDBY mode feature for MediaTek’s 20nm Smartphone SoC product line.

2. Worked on the post-Silicon Bring-up, and on detailed validation for the top CLKGEN and for a custom MediaTek interface protocol.

3. Found critical issues during PoR sequence of 20nm Smartphone SoC product line, worked on the design fixes.

4. Owned the SoC top level CLOCK and RESET design module, worked closely with PD team, worked on the functional constraints for the design change and fixes.

AUVIZ SYSTEMS INDIA PVT LTD, HYDERABAD

STAFF DESIGN ENGINEER AUGUST, 2014 - NOVEMBER, 2014

5. Developed micro-architectures for BLAS (Basic Linear Algebra subroutine) functions on Xilinx Vertex-7, guided a team of headcount 3 to successfully implement 3 BLAS functions: GEMM (General Matrix-Matrix Multiplication), SYRK (Symmetric

Rank-K update) and GR (Finding Rotation Matrix).

TEXAS INSTRUMENTS INDIA PVT LTD, BANGALORE

SENIOR DIGITAL DESIGN ENGINEER DECEMBER, 2011 - JULY, 2014

• SoC design and implementations for 3G/LTE small cell base station integrated transceiver (on 45nm technology).

Designed the SoC memory map on 4GB address space (from CORTEXM4F) for the platform product.

Designed the memory sub system on the interconnect matrix.

Designed the AHBlite based Interconnect BUS Matrix Architecture to meet the latency requirements from external BUS

masters on the multilayer interconnect matrix.

Architected and designed a dynamic weighted Round Robin Arbitration on the AHB Interconnect Matrix.

Designed Security features on the memory subsystem on Interconnect Matrix.

• Key SoC/IP Designs Delivered:

LMS fixed point design.

Designed the RESET-GEN FSM module.

Designed ECC System architecture, designed the system glue logic to handle SEC/DED.

Designed from scratch the SEC-DEC based ECC architecture for on chip memories.

Implemented the design to meet different data sizes 8/16/32 bit without having the penalty of Read-Modify Write.

• Worked as a STA engineer to own and deliver the synthesis and STA constraints. The key STA challenges accomplished are:

Developed the timing constraints for new design blocks with complex clocking, updated the block/chip level constraints

for design updates for SYNTHESIS, post-CTS, post-route-post-CTS STA runs.

Debugged, Analyzed the Timing runs and identified the timing fixes.

Worked on the What-if/Virtual ECO flows to support the PD team.

Owned the responsibility for developing the IO constraints for SPI, JTAG, TEST interface to memory and the Custom module

of the TI design.

MAXIM INDIA INTEGRATED CIRCUIT DESIGN PVT LTD,BANGALORE

MEMBER TECHNICAL STAFF DECEMBER, 2008 - NOVEMBER, 2011

• Built the HART CPFSK 1200bps modem receiver system architecture on matlab. Implemented the receiver module blocks in Verilog (on 0.18nm). The key challenges accomplished:

Designed 1200bps HART CPFKS Modem Digital Receive signal chain algorithm in MATLAB.

Modeled the System architecture in MATLAB, Defined the spec. for ext. filter cut-off freq., attenuation rate, ADC resolution, Digital Process Block Gains, Carrier Detect Assert/De-assert Thresholds.

Used MATLAB extensively to design 6th order BandPass Filter (3 cascaded 2nd order IIR filters), worked on 16-bit (Q1.15) quantized fixed point arithmetic. The key modules on the receive path designed are the zero-crossing detector, carrier-detect module and the moving average filter.

• Designed and integrated LCD/TFT display controller for ARM7TDMI SoC (on 65nm). The key challenges accomplished:

Defining the Specification and Micro-Architecture of 4096x4096 (max) pixel, 24-bit Color LCD Controller supporting all types of display panel timings.

Designing 4096x4096 pixels (max), 24-bit Color LCD controller supporting all types of TFT and STN Panels.

Analyzing the External Memory (DDR) latency requirements, bus bandwidth taken by the TFT controller/Frame Buffer and bandwidth available to the blocks sharing the bus with TFT controller while architecting the system.

Designing the Gray Scale Modulation for STN Panels to achieve color resolutions up to 16K.

• Owned the system architect and digital design/RTL implementation of Trusted/Secured Display Emulator for the secured financial terminals.

Built the system architecture and defined the specification for the Secured TFT display on financial terminals.

Designed from scratch the TFT Emulator for Trusted Display Contents and integrated into ARM7TDMI subsystem.

• Designed the Magnetic Card Reader decode system (on 180nm).

Designed an all new DPLL based Clock/Data decode system for magnetic card reader, modelled the decoding system in MATLAB.

• Designed an Asynchronous FSM for power sequencer using Digital full Custom Circuit

Synthesized the Asynchronous FSM into RS flops, full custom circuit designed in digital CMOS 180nm technology.

MAXIM INDIA INTEGRATED CIRCUIT DESIGN PVT LTD,BANGALORE

ASSOCIATE MEMBER TECHNICAL STAFF SEPTEMBER, 2006 - DECEMBER, 2008

• Worked as an IP Design Engineer. Designed the following IPs from scratch:

AHB Master interface for Display Subsystems to perform DMA transactions through memory controller

I2C Master/Slave Controller IP

SPI Slave Controller Core IP

LIN 2.1 compliant UART

GRADUATE INTERN

INTEL TECHNOLOGIES INDIA PVT LTD, BANGALORE MARCH, 2005 - AUGUST, 2005

• Worked on Whitefield processor/L2 Cache CMOS full custom circuit design in 65nm technology.

GRADUATE ENGINEER TRAINEE

BHARTI TELNET PVT LTD, CHENNAI JUNE, 2002 - OCTOBER, 2002

• Installation, Configuration of Network switches for Managed Leased Line Networks.

ACADEMIC BACKGROUND

• MS(R) in Microelectronics and VLSI Design from CEDT, Indian Institute of Science, Bangalore [January, 2004 - June, 2008]

MS Thesis: A Novel Higher Order Noise Shaping Sigma-Delta Modulator Implementation using SI (Switched Current) circuit

technique in 180nm CMOS technology.

• BE in Applied Electronics and Instrumentation Engineering from National Institute of Technology, Rourkela [August, 1998 - April, 2002]

Major Project: A High Resolution, 6MHz Comparator Design in 1.2um CMOS technology.

• Member, IEEE Circuit and Systems Society, Seoul Section



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