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Analog design physical design verification and testing

Location:
Guwahati, Assam, India
Salary:
5l
Posted:
August 14, 2018

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Resume:

NAME : SUSHANTA BISWASARMA

ID NO : **MV**

DEGREE : Master of Engineering

BRANCH : VLSI Design

COLLEGE : PSG College of Technology, Coimbatore.

Father’s name NIPENDRA BISWASARMA Permanent Address Gender Male

th

House No-5, near Q/R No-102

Date of Birth 28 may 1989 A, Pandu College Gate,

Languages known English, Hindi, Bengali, Assamese Ghy-12,Assam Email ac6nzk@r.postjobfree.com

Mobile +91-887*******,+91-600*******

ACADEMIC RECORD

CLASS/

COURSE

NAME OF THE

INSTITUTION

BOARD OF

STUDY

YEAR OF

PASSING

MARKS /CGPA

ME(VLSI

Design)

PSG College of Technology,

Coimbatore.

Anna University

2018

6.93

BTECH

(ECE)

Majhighariani Institute of

Technology and Science,

RAYAGADA

BPUT,ROURKELA

2013

6.8

INTE

R

Pandu college,Ghy12

Assam

AHSEC

2008

52

X

Bidyamandir higher sec

School, ghy, Assam

SEBA

2005

60

* CGPA (out of 10)

SKILL SET

Hardware Description

Languages

Programming Language

Scripting Languages

Verilog, System Verilog, VHDL

Basic of C, Data structure, C++, Core JAVA

Perl, Python

Tools

Hardware package

Application Software:

Cadence- virtuoso, NC-launch,Encounter,synopsys

Xilinx- ISE 14.2

Tanner- S-Edit, TSPICE

Xilinx Spartan 3E Board

Microsoft Office, Matlab, DBMS, HTML

AREA OF INTEREST:

ANALOG circuits Analysis And Layout Design

Physical Design and Verification

Low Power Analysis of VLSI circuits

Digital Design Verification & Testing

Computer Aided Design of VLSI systems

Webpage Making

Project On Analog Circuits:

Design of Power Efficient Phase Locked Loop(Digital, Analog, and Mixed signal)

Design of A 10-MHz Switched Capacitor Low-Pass Filter for Wireless Application

Low Power High Gain Bandwidth Opamp in Low Cost 180 nm Bulk CMOS Technology

Design of PLL With High Gain OTA Based Low Pass Filter.

Implement An Energy Efficient SAR-ADC and Phase Locked Loop Using Verilog A Basic Analog Circuits Design:

Self Biasingcascode current mirror

Basic op-amp structure analysis

Successive approximation register design with 180 nm technology

A Highly EMI-immune Folded Cascode Op-Amp

Designing OP-amp for low-voltage, High-speed, High accuracy Analog- to- Digital Converters

Analog Circuits Layout:

Basic Inverter

CS Amplifier

Physical Design For Digital Circuits(Using Cadence): Vending Machine, BCD Counter, IIR filter, Pulse Generator, UART, J-K Flipflop, ALU

(With suitable positive slack time and with no Setup and Hold violation) Physical Design For Different Processor(Using Cadence and Synopsys):

16 Bit Risc Processor

32 Bit Risc Processor

Mips Processor

Rocket Chip Generator

Functional Verification and CODE Coverage(Mentor Graphics): UART, Comparator, Sequence Detector, Simple Memory Design, IIR Filter TESTING(using xillinx):

Optimization of power and area using majority voter based fault tolerant VLSI circuits Graphic Design

Windows XP 7, Linux

Networking +

Professional course

Operating System

Computer certified

DFT Based Testing(Cadence):

Vending Machine, BCD Counter, IIR Filter, FIR Filter, Pulse Generator, UART, Simple Counter, Traffic light controller, Sequence Detector FPGA Based Design(Using Xilinx)

Vending Machine, BCD Counter, IIR Filter, FIR Filter, Pulse Generator, UART, Simple Counter, Traffic light controller, Sequence Detector Others(matlab)

Applied Various types of low power Techniques on Digital circuits Implementation of simulated annealing for minimizing floorplan area using MATLAB Genetic algorithm for reduced floor plan using MATLAB Surveying on Different current topics:

EMBEDED Based Design:

Google Lens

Driverless Car

Solar cell (Increase power Efficiency)

Worked on Different ARM Based processor

Soc Based Design and Verification

PROJECT (B-TECH)

Tiny Dew Sensor For Weather Monitoring (MINI PROJECT)

Weather Monitoring System Using GSM With SMS Alert (MAJOR PROJECT) SEMINAR APPEARED:

Higher Electron Mobility Transistor (TOPIC)

High Level Modelling of All Digital Phase Locked Loop(National Conference at PSG Tech) IEEE COURSES:

Fundamentals of Static Timing Analysis.

RTL Design Using Verilog.

WORKSHOPS ATTENDED:

Attended workshop on “ASIC design flow using Cadence” at PSG College of Technology.

ACADEMIC ACHIEVEMENTS:

Gate qualified in 2014, 2016 and 2018 Secured 430 score with 4925 Rank in GATE 2018 (ECE).

Attended Math Olympiad in PSG Tech and Secured 14th Place PERSONAL TRAITS:

Zeal to learn new things.

Hard working with systematic planning

Self Motive

Ability to deal with the people diplomatically and be novel.

Ability to handle stress with cool attitude n ease Hobbies: Listening Music, Reading Books, Cooking, Travelling new places n exploring their culture, Playing Pc games

DECLARATION

I,SushantaBiswasarma, do hereby confirm that the information given above is true to the best of my knowledge.

Place: Coimbatore

Date: (SushantaBiswasarma)



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