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Designer Development

Location:
Jasper, Georgia, United States
Posted:
August 12, 2018

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Resume:

Dale DAVISDAVIS

404-***-****

ac6mzi@r.postjobfree.com

https://www.linkedin.com/in/dale-davis-a6073495/

Summary:

Printed Circuit Designer with more than 25 years of experience.

Emphasis on schematic entry, PCB layout, penalization, and post processing.

Designs include high-speed, differential pairs, impedance control, RF, analog, digital, shielding, EMI, high voltage FPGA/Memory DDR4LV

BGAs, micro strip, strip line, single to multilayer stackups with thru-blind-buried-micro vias

Created and implemented technical standards and engineering change procedures and document control.

Coordinated ordering, fabrication and delivery of PCBs

Handled problems from diverse input in regards to layout, fabrication, thermal and assembly in conjunctions with Solidworks and Auto-Cad

Skills/Certificates

Cadence Allegro Professional /OrCad Schematic 16.6 software

Cadence Ultra Librarian Beta Ver 17.2

Mentor Graphics Dxdesigner Version 7.9.5

Cam350 Version 9.0

Design Check Software Valor Version 9.0

Standards Ansi 14.5Y, ANSI 32.2Y IPC-275, IPC-2221A IPC-2223B IPC-2615, IPC-4203, IPC-7095B,IPC-A-610D, IPC-D-279 IPC-D-330 IPC-SM-782, Mil-P-55110D

Professional Experience:

Advanced Signal Dynamics Atlanta, GA

6/1/2017 to Current

Senior Hardware PCB Designer

Using Mentor Graphics Expedition EEVX2.1 with this legacy tool suite. Double sided 0201 Micro via FPGA 20nm all designs involved routed Platform design, transmission Line routing.

Mentor using HDI layer type environments in 20 to 35 layer stackups at 2.4 to 3.4 mm thick. All designs Diff pairs and IPI line with clock speeds development with designs involving signal integrity verification. Typical 4/4 routing with 0.4mm BGA device with Micro-Controllers on ALIVH and Vertual Pin type boards. Processor development Xilinx Ver 7, Marvell, Vertex 6, Typical Stacked micro via size 250/80 plus blind/buried application.

Draper Labs Cambridge, MA

4/31/2015 To 04/31//2016

Senior PCB Designer

Using Mentor Graphics Expedition 7.9.4 Dxdesigner Dxdatabook with this legacy tool suite. Double sided designs using 0201 Micro via BGA all designs involved routed Memory DDR-2 and DDR-3, Transmission Line routing for Military Product development using CES and ICES formats using Altera chip sets. Environments involve the Mentor HDI layer type environments in 10 to 12 layer.

All designs were with Diff pairs and MIPI line with clock speeds development with designs involving signal integrity verification. Typical 4/4 routing with .4mmFPGA and Memory DDR3 DDR4 devices on ALIVH type boards.

EF Johnson Corporation Dallas Texas

09/13/2014 -04/30/2015

Senior PCB Designer

Using Mentor Graphics Expedition 7.9.5 Dxdesigner from conversitions Mentor graphic PADs software with DxDesigner. Double sided designs using 0201 Micro via BGA all designs involved routed Memory DDR-2 and DDR-3, Transmission Line routing for Commercial Police and EMS Radio Systems including Product development for Rack and Panel development.

Experience working Flex Designs, digital/Analog, and various mixed signal designs. These designs included technologies most routing using MST, Chain, T-shape routing development along with and not limited to vias at 4/4 trace and space.Experience using Downstream Blue Print and Altium Gerber verification software Viewer. All Designs are of 1GHz to 3GHz with 2 to 12 Layers using Orcad Schematic Capture..

L3 Communication Salt Lake City Utah

4/13/2014 – 11/01/2014

Senior PCB Designer

Using Mentor Graphics Expedition 7.9.5 Dxdesigner Dxdatabook with this legacy tool suite. Double sided designs using 0201 Micro via BGA all designs involved routed Memory DDR-2 and DDR-3, Transmission Line routing for Military Product development using CES and ICES formats using Altera chip sets.

Experience working power supplies, backplanes, digital/Analog, and various mixed signal designs. These designs included technologies such as high speed, HDI, via in pad. Using CES to established setup in Netline ordering involving Load and Source device ordering, most routing using MST, Chain, T-shape routing development along with SERDES data Address and control signals .

Experience using Downstream Blue Print documentation software, along with IGI Checkmate Gerber Viewer. All Designs are of 10 GHz to 30 GHz with 16 to 22 Layers.

Advanced Signal Dynamics Atlanta, GA

2/1/2014 to 4/7/2014

Senior Hardware PCB Designer

Using Mentor Graphics Expedition 7.9.5 Dxdesigner Dxdatabook with this legacy tool suite. Double sided 0201 Micro via BGA all designs involved routed Memory DDR-2 and DDR-3, Transmission Line routing.

Mentor Graphics to Cadence version 16.0 CIS conversions using HDI layer type environments in 10 to 12 layer stackups at 1.6 to 2.4 mm thick. Board bending and arching. All designs Diff pairs and IPI line with clock speeds development with designs involving signal integrity verification. Typical 4/4 routing with0.4mm BGA devices on ALIVH type boards. Processor development Xilinx, Marvell, Vertex 6, Typical Stacked micro via size 250/80 plus blind/buried application.

Qualcomm San Diego, CA

7/7/2013 TO 11/15/2013

Senior Hardware PCB Designer

Using Mentor Graphics Expedition Dxdesigner Dxdatabook produced FFA (CES) Handset designs these boards require mastery in Digital Processor RF as well as Power Control devices. Also supported Emulators and 1500 pin BGA High Density digital designs in the areas of 12 to 14 layers with .4mm pitch devices. Majority of designs where Double sided 0201 Micro Via BGA All designs involved routed Fuel Gauge and CSI-2 CSI-3 and DSI-2 development.

Environments involve the Mentor HDI layer type environments in 10 to 12 layer. All designs were with Diff pairs and MIPI line with clock speeds development with designs involving signal integrity verification. Typical 4/4 routing with .4mm BGA devices on ALIVH type boards. Processor development Qualcomm S4 Snap Dragon along with and not limited to OMAP Design work.

Development and design for PMIC boards that increase power for the S4 Snap Dragon which is mostly power and HDMI.

Advanced Signal Dynamics Atlanta, GA

2/1/2013 to 6/1/2013

Senior Hardware PCB Designer

Using Mentor Graphics Expedition 7.9.2 Dxdesigner Dxdatabook with this legacy tool suite. Double sided 0201 Micro via BGA all designs involved routed Memory DDR-2 and DDR-3, had coil routing.

Current environment involves the Mentor to Cadence version 16.0 CIS conversions using HDI layer type environments in 10 to 12 layer stackups at 1.6 to 2.4 mm thick with some layers removed for Board bending and arching. All designs Diff pairs and MIPI line with clock speeds development with designs involving signal integrity verification. Typical 4/4 routing with0.4mm BGA devices on ALIVH type boards. Processor development Xilinx, Marvell, Vertex 6, Typical Stacked micro via size 250/80 plus blind/buried application.

All boards are of HDI design in areas with Accelerometers, GPS, and average processors pin devices of 1500 to 1700 hundred pin devices.

Blackberry Irving, TX (Direct Employee)

12/1/2008 TO 10/28/2012

Senior PCB Designer

Using Mentor Graphics Board-station/Expedition WG2007.5Dxdesigner, Dxdatabook /Valor Genesis 9.0 with Zuken Redac 13.0 conversions from this legacy tool suite. All designs involved routed CSI,DSI,DDR3, using Reuse in most design application

Providing Memory, HDI 3-4-3 layer type environments using 10 to 12 layer stack ups. All designs 50 ohm to 100 ohm and MIPI line with 26 to 32 MHz clock speeds development with designs involving signal integrity verification and RF cans via for reference plane applications. Double Team and Dividing designs in most design forms using Conversions from Mentor to Zuken.

Typical 4/4 routing with 0.4mm BGA devices on ALIVH type boards. Most design constraints to 1 Gig environments this also includes USB 3.0 routing class.All new processor development Xilinx, Marvell, Vertex 6, Qualcomm TI, with RF Platform designs.

Draper Labs Cambridge, MA

9/3/2007 TO 8/29/2008

Senior PCB Designer

Using Mentor Graphics WG2005.SP3 with DxDatabook and Dashboard used to perform flex and Rigid Flex designs for the Trident Missile update program. Primary work was with flight-testing applications.

Interfaced with tools such as AutoCAD 2006 Microsoft Office and Excel 2007. Most design applications involved blind/buried vias, Copper balance applications along with DFT criteria. Using DxDatabook and DxDesigner with Pinnacle and Accent Lx software for Mentor Graphics Expedition.

Most work typical 50 ohm stack up with Split planes for evaluations of Signal Integrity and Splits Over planes application for RF designs with Accelerometers, GPS, and IMU development. All designs performed with ROHs lead free applications.

Aerojet Sacramento, CA

8/1/2006 TO 4/1/2007

Senior Hardware PCB Designer

In conjunctions with the Mentor Graphics Tool with OrCad 15.5 schematic capture responsible for development of electronic circuit boards applications for project Orion. All designs met NASA and Lockheed standards.

Experience with different types of packaging including multi-layer, SMT, BGA, high density printed circuit boards per IPC requirements.

Agilent Technologies Vancouver, Canada

8/1/2005 TO 6/1/2006

Senior Hardware PCB Designer

Primary position involved creating, designing and developing a PCB capable of implementing a specific program through Auto-Active RE using 1517 and 1552 pin FPGAs.DMA chipsets in conjunction with B and Q CODEC types of technology.

Design applications were from a 1 to 26 layer environments, laser vias and 4 /4 mils traces. Established and maintained designs using Nokia standards which included IPC 2220, 2221, 2222.

Nokia Mobile Devices San Diego, CA

8/1/2004 TO 7/5/2005

Senior Hardware PCB Designer

Primary position involved creating, designing and developing a PCB capable of implementing a specific program for Product/Platform phone technologies. All worked performed from PLATFORM development standards.

Using Auto-Active RE using 1517 and 1552 pin FPGAs with RAP-CDMA chipsets in conjunction with B and Q CODEC types of technology.

Education

IPC Certified Nov 2003 (CID)

Devry University 2006

Other Electrical Engineering Technology Alpharetta, GA

70 hours

Reinhardt University

Other Business Waleska, GA

Business 80 Hours



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