Electrical Engineering Assistant

SRI HARSHA AMERNENI

MS – EE 806-***-**** *****************@*****.*** LinkedIn: www.linkedin.com/in/sriharshaamerneni Graduate with Master of Science in Electrical Engineering (May 2018) and with over 2 years of work experience, as Electronics Lab Assistant. While my excellent technical skills are the strength of my resume, timely and accurate communications was also key to my past successes. Looking forward to bringing experiences, skills and scholastic successes (3.67 GPA) into a new career. Few of my prominent skills include:

• Test Automation using LabView

• Test Development on NI STS (ATE)

• Experience with CISC and RISC Processor

Designing

• Knowledge on Statistical Process Control

• Circuit Design and Layout Experience

• Hands on experience with Hardware and

Software Tools

EDUCATION

Master of Science in Electrical Engineering August 2016 – May 2018 Texas Tech University, Lubbock, TX GPA – 3.67/4.0

Bachelor of Technology in Electronics and Communication Engineering June 2011 – May 2015 Jawaharlal Nehru Technological University, India GPA – 3.8/4.0 TECHNICAL SKILLS

Languages (including HDL’s): C, Verilog, VHDL, MATLAB, System Verilog, C++, Python. Tools: NI LabView, CADENCE, HSPICE, Xilinx ISE Design Suite, ModelSim, NI AWR, Synopsys Design Vision, Synopsys IC Compiler, Eagle CAD.

Test Equipment: NI Savage ATE, PXIe – 1075, NI MyDAQ, Keithley 24xx SMU, Agilent Oscilloscopes, Dual Power Supplies, Arbitrary waveform generator, Digital Multimeter, Agilent Network Analyzer and Keysight Signal Analyzer.

Data Analysis: JMP and Microsoft Excel.

Platforms: Windows and NI Test Stand.

WORK EXPERIENCE

Texas Tech University – Teaching Assistant September 2016 – May 2018

• Taught, Graded and monitored the students’ progress in their Projects and Assignments.

• Conducted tutorial sessions for the students on using the Verilog Programming and Assembly Language Coding.

• Guided the Students with their Design Project of CISC and RISC Processors using Verilog Programming.

• Also, Demonstrated the techniques in developing the automation codes in LabView for the Testing of Mixed Signal IC on NI STS (ATE) and NI PXie - 1075.

• Launched Mentoring sessions for students to enhance their growth mindset in reaching success and harmony in team settings.

Avanthi Institute of Engineering & Technology – Teaching Assistant/Lab Assistant July 2015 – June 2016

• Lab Instructor for VLSI Design and Electronic Circuits.

• Created new Projects and set up the VLSI lab.

• Helped the Students with their mini Projects using Embedded Systems.

• Demonstrated the Lab Safety Techniques and supervised the experiments in the electronic circuits Lab to ensure the safety of the students.

• Operation and regular maintenance of the Lab Equipment. ACHIEVEMENTS & CERTIFICATIONS

• Awarded with Best Design Project from Dr. Changzhi Li at Texas Tech University for the Design Project of a Temperature Sensor from a PTAT current Generator Circuit using 0.6μm CMOS Technology in CADENCE.

• Awarded with Seacat Scholarship from the Department of Electrical and Computer Engineering at Texas Tech University for the entire grad school.

• Awarded with Gold Medal during my Under Graduation from the Department of Electronics and Communication Engineering for emerging as the topper in the batch 2011-2015.

• Passed the E.I.T (Engineer in Training)/FE exam from Texas PE Board. The associated license number is 18-842- 12.

ACADEMIC PROJECTS

Testing of 8-bit, μP Compatible ADC080

Performed all the basic tests to evaluate the ADC 0802 performance Characteristics using the NI STS (ATE), NI PXIe 1075 and on Bench Equipment Using Keithley 24xx series instruments, Agilent E3648A, NI Virtual Bench, MSO6054A Oscilloscope. Analyzed the results for calculating Cp, Cpk, and percentage GRR for the obtained measurements using the JMP Software and evaluated the stability of the measurements derived from the tests. Also, evaluated the Tester - Tester Correlation for the obtained measurements between the ATE, PXIe 1075 and Bench Equipment.

Design, Simulate, Implement & Test of 2.45 GHz Low Noise Amplifier Designed, simulated and implemented a 2.45GHz LNA on Copper FR4 clad board in AWR software to meet the given specifications and tested the performance using Network Analyzer and Signal Analyzer. Testing of Low Power Current Output DAC0800LC

Validated datasheet by testing the AC and DC Characteristics of DAC0800LC. Developed code for automating test procedures in LabView, NI PXIe 1075, NI Switch Matrix, Bench Equipment, analyzed the results and calculated the Percentage GRR and six-sigma quality using Matlab. Design of a Temperature Sensor from a PTAT Current Generator Circuit in CADENCE Designed a Temperature sensor using PTAT Current Generator circuit on CADENCE and performed the stability analysis and drew the layout for the proposed design. The simulation results obtained from the design were 52.79 of phase margin and 18450μm2 area for the layout. Design of Common Mode Feedback Fully Differential Amplifier using AMI06 CMOS Process Designed an Operational Transconductance Amplifier and connected the outputs of OTA to the common mode feedback paths to make it fully differential and to stabilize the common mode output voltage. Stability analysis was performed on the proposed design and simulation results that were obtained are 37.64dB of Gain and 89.68 of Phase Margin. Also, designed the Layout in Cadence with an area of 6648.72 nm2. Testing of 8-line to 1-line data Multiplexer SN74ALS151 Automated LabVIEW code modules into a test stand sequence for continuity, leakage current, power consumption, functionality, VOH & VOL, VIH & VIL with a pin map file. Tested with Agilent Oscilloscope for propagation delay and rise & fall times. Also, analyzed the results for the tester – tester correlation on PXIe 1075, Keithley and NI MyDAQ. Used process capability parameters Cp, Cpk & percentage GRR for statistical analysis on data reliability.

Design of Pipelined RISC CPU using Verilog HDL

Developed a modular based Verilog Model for pipelined RISC CPU. Designed modified register file, function unit, and instruction decoder modules separately and designed the main module which instantiates each of these submodules in a pipeline structure.

Logic Gate Based Schmitt Trigger Design in 32nm FinFET and 90nm Bulk CMOS Logic Gate Based Schmitt Trigger was designed to realize 3 input NAND, NOR and XNOR functions in 32nm FinFET and 90nm Bulk CMOS ASUPTM technology using HSpice. Design of a Pass Transistor Logic Based Full Adder and 7:3 Compressor Using 32nm CNTFET Designed a Full Adder and 7:3 Compressor Using 32nm CNTFET and 32nm Bulk CMOS Technology on HSpice. Also measured the Peak Power, Delay and Power Delay Product from the Obtained simulations and performed the comparative analysis between 32nm CNTFET and 32nm Bulk CMOS.

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