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Engineer Design

Minneapolis, Minnesota, 55435, United States
February 19, 2018

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Morris Zakaim

**** **** *** *, ***. ***, Edina, MN 55435

Tel: (917) ***-**** Email:

Position Desired

Digital Design Engineer (contract only)


MS in Electrical Engineering, May 1996, NYU Tandon School of Engineering (Formerly Polytechnic University)

BS in Electrical Engineering, computer option, May 1991, Tufts University

Summary of Skills

Digital and high-speed board design from concept and requirement generation to schematic capture, layout guidelines, board bring up, debugging, functional testing, as well as hardware/software integration.

FPGA design in VHDL, Verilog and SystemVerilog (for design only), simulation, synthesis, place and route, timing closure, and debugging using Actel, Xilinx, Altera and Lattice FPGAs and tools (Vivado, ISE, Quartus, Lattice Diamond) as well as QuestaSim, ModelSim, Aldec and Synplicity.

Experience with PADS DX Designer VX.2, Mentor Graphics Expedition, OrCad and Cadence schematic capture tools.

Microcontroller and microprocessor system design and programming using NXP QorIQ LS1043A, MPC860, MC68HC11 and I87C52.

Programming in C, assembly, php and MySQL.

Experience with logic analyzers and digital scopes.

DO-254 compliant documentation using Telelogic Doors and SourceSafe.

Personal Projects

January 2017 to Present

NXP QorIQ LS1043A Single-Board Computer

Designed a Single-Board Computer loosely based on the NXP QorIQ LS1043 Reference Design Board. The design consists of:

NXP LS1043A 64-bit, Quad-Core ARM Cortex-A53 processor

NXP MK22FX512VLH12 microcontroller (used for MSIS Debug Access Port)

Lattice LCMXO1200C used as system controller CPLD

256MB Parallel NOR Flash, 4Gb SLC NAND Flash, 4GB DDR4 (32-bit data bus)

X1 PCIe port, X1 PCIe link for FPGA mezzanine card

10Gbps (10GBASE-T) and 1Gbps Ethernet ports

Two UARTS and two USB ports

Currently compiling the layout guidelines document.

Xilinx DDR4 MIG Tester

Designed (SystemVerilog/Vivado 2017.2) a DDR4 test module to drive a MIG IP core, tailored to the Xilinx KCU105 evaluation kit EDY4016AABG-DR-F-D DDR4 memory. This module:

Continuously writes and reads back the entire MIG memory space and stops on the first encountered error

Memory content is produced using a 512-bit PRBS generator

Can optionally write and read back (continually) a given address range

Can optionally (DIP switch) inject and detect errors at 15 preselected memory locations

Xilinx Aurora Serial Link Tester

Designed (SystemVerilog/Vivado 2017.2) a 10Gbps Aurora serial link test module to drive a single-lane Aurora IP core implemented on the Xilinx KCU105 evaluation kit. The choice of lane numbers and line speed was limited to the single lane available on the evaluation kit through a set of SMA connectors, and the bandwidth of said connectors (16 GHz). The transmit lane was looped back to the receive lane using Amphenol SMA RF cables. This module:

Transmits and receives a fixed number of frames and stops on the first encountered error

Frame content is produced using a 64-bit PRBS generator

Each frame can contain a predetermined number of 64-bit words

Can optionally (DIP switch) inject and detect errors at 15 preselected frames/word-positions

Work Experience: Contract positions

February 2017 to

September 2017

Contract engineer at General Dynamics Mission Systems, Bloomington, MN. Responsibilities:

Resolved a number of Problem Reports (PR) related to an Altera Arria V FPGA/CPU (5ASXFB3G4F35I3N) board. Problems included:

A periodic reset generated by the processor after a manual reset.

Processor getting hung up after a manual reset.

Trouble shooting a UART newly added to the FPGA design.

Compiled a User's guide for above FPGA/CPU board.

Designed a test circuit board to route a number of signals from a single board computer to a D-Sub test connector.

Updated an existing CCA schematic to eliminate necessary cuts & jumpers, replace two Gigabit Ethernet Pulse transformers with a single equivalent dual transformer to open up room on the CCA to move a few board components away from a connector to ease reworking/repairing of the CCA.

Provided general CCA design services such as schematic capture/modification, schematic symbol creation, design reviews, component requests, ...

August 2015 to

April 2016

Contract engineer at SEAKR Engineering, Centennial, CO. Responsibilities:

Designed, simulated and tested the User Core module of SEAKR's DSTE high-speed test card FPGA. The FPGA design includes two Serial Rapid IO (SRIO) input ports, four 10 Gigabit/s Ethernet output ports and one 100/10 Mbps Ethernet port for software control of the test card. It also includes the necessary clock and reset logic. Above functions are implemented using in-house and Xilinx IP cores. The function of the User Core module is to receive SRIO packets via Slave AXI4-Stream interface of the SRIO IP Cores, recognize packet types and perform some or all of the following, on-the-fly, based on the packet type:

Process only certain type of packets and discard others.

Generate an error pulse upon reception of irrelevant types of packets.

Combine six packets of a specific type into one large packet.

Strip unwanted data and append additional necessary data to processed packets.

Route processed packets to outgoing 10 Gigabits/s ports via master AXI4-Stream interfaces.

Provide interrupt, command and status registers for software interface.

February 2014 to

July 2015

Contract engineer at Agilent Technologies, Santa Clara, CA. Responsibilities:

Eliminated timing violations in Agilent Technologies' DSP10 FPGA by adding pipelined stages, duplicating signals, adding placement constraints and over-constraining one clock signal.

Made minor modifications to the DSP10 FPGA design as needed to meet performance requirements.

Added a new module to the DSP10 FPGA to unpack 22-bit A/D integers stored in 32-bit words in memory, on-the-fly, before passing them on to the PCIe interface to be transmitted to a processor board.

Completed DSP10 FPGA documentation.

Made minor modifications to three other FPGA designs as needed to meet requirements or improve performance.

March 2013 to

December 2013

Contract engineer at Covidien, Boulder, CO. Responsibilities:

Maintained, documented and added new features to three Xilinx Spartan-6 FPGA designs/testbenches in Covidien’s ForceTriad Energy Platform to support the upgrade effort to an all RoHS system.

April 2012 to

December 2012

Contract engineer at Omron Scientific Technologies, Inc. Fremont, CA. Responsibilities:

Designed the following image processing FPGA modules in VHDL:

High Dynamic Range Fusion: combines two images taken with high and low exposures using a proprietary formula to estimate the intensity of each pixel in the combined image. Debugged this module using ChipScope.

Zone Comparator: compares a boundary stream with a disparity stream to determine if a given pixel is inside or outside of the given boundary.

Dynamic Range Check: flags pixels that are too bright or dim.

NCC Reference Marker Search: searches for a reference marker, placed in the field of view of the camera, by calculating a normalized cross-correlations (NCC) between the template of the marker, stored in memory, and equal sized portions of the search area dedicated to it, in sequential order. The coordinates of the portion with the highest NCC is then reported as the coordinates of the marker along with winning area pixel values and other information for processing. This module also generates an error flag if NCC calculations take too long.

Fixed-Pattern Noise Removal: removes the dark image pixel values, compressed and stored in processor memory, from the pixel values received from the corresponding camera.

July 2011 to

March 2012

Contract engineer at CPU Technology Inc. Pleasanton, CA. Responsibilities:

Compiled a board-level design requirements document.

Contributed to bring up and trouble shooting of a CPU board including PCI, 10Mbps Ethernet, DDR2 SDRAM, FLASH and FPGA. Modified FPGA design as needed in Verilog.

Created self-checking, linear testbenches in Verilog to simulate and debug various FPGA modules. Testbenches used text files as the source of address, data, reset value and data mask for testbenches.

November 2010 to

December 2010

Contract engineer at DornerWorks, Ltd. Grand Rapids, Michigan. Responsibilities:

Selected an appropriate Altera FPGA and a development kit for the DornerWorks, in-house R&D, Multi-LCD Single Board Computer project. The function of the board is to display video from up to four digital cameras on their associated TFT LCD display, under the control of a PIC microcontroller.

Started the FPGA design using Altera video IP cores with Quartus and ModelSim FPGA design tools. Set up FPGA project and simulation environment in accordance with DornerWorks internal processes and ran preliminary simulations. Handed off the design to a co-worker for completion, in order to work on a different project which was cancelled by DornerWorks client.

June 2009 to

January 2010

Contract engineer at Telephonics Corporation, Farmingdale, New York. Responsibilities:

Designed a fully automated VHDL testbench for an FPGA implemented with a Xilinx Virtex IV. Testbench included VME bus and Analog Devices Blackfin DSP processor read/write procedures as well as interrupt status and acknowledge procedures. These procedures were used to exercise the FPGA’s memory map and inter-processor communication function and to mimic software set up and testing of the inter-processor communication link at power-up. The testbench also provided automatic verification of the simulation results and generated error messages to the simulator log window. This testbench was extensively used for regression testing of the FPGA design during development.

Contributed to the FPGA development by correcting some of the errors discovered using above testbench.

March 2008 to

December 2008

Contract engineer at Telephonics Corporation, Farmingdale, New York. Responsibilities:

Designed a front panel controller board. The design included switching and linear regulators for various voltages used by on-board FPGAs, two Xilinx Virtex IV FPGAs, one to read switch status and control the LEDs and a character display on the front panel, the other to monitor switches and LEDs independently from the controller FPGA. Both FPGAs interfaced with the rest of the system through an RS485 serial bus. The controller board also had interface circuitry for a number of discrete input and outputs as well as a CODEC. Various test connectors and a JTAG test and configuration connector was also provided.

Designed a CPLD in VHDL for an audio board to control audio routing/switching and communicate with the rest of the system using a serial link. It also commanded a DTMF chip to generate a 300mS test tone used to verify audio paths. Tested the design with a VHDL testbench and 100% code coverage. Optimized the design from 94% utilization down to 78% to meet maximum resource usage requirements.

Designed three VHDL modules used by other FPGAs in the system. Designs included serial transmitter/receivers as well as simulation models for EPROMs and dual-port RAMs. All modules were simulated with VHDL testbenches with 100% code coverage.

Documented above CPLD design in compliance with DO-254 requirements using Telelogic DOORS. Other documents (Visio, MS Word) were maintained on SourceSafe.

May 2006 to

August 2007

Contract engineer at JDSU, Germantown, Maryland. Responsibilities:

Provided services in areas of schematic capture, design review and test of a jitter/wander generation/measurement product.

March 2005 to

April 2006

Contract engineer at Northrop Grumman, Laser Systems, Apopka, Florida. Responsibilities:

Created Design Requirement Documents and Interface Control Documents for various circuit boards.

Created the system interconnect schematic for a laser target-location/designation system.

Created a test harness schematic for above mentioned system.

Designed circuit boards to replace existing wire-wrapped boards in multiple test fixtures.

Re-designed a microcontroller test fixture board which had an obsolete microcontroller with an almost identical, newer version of the microcontroller.

October 2003 to

January 2005

Contract engineer at Northrop Grumman, Baltimore, Maryland. Responsibilities:

Designed a PCI Mezzanine card with a PLX technology PCI bridge chip, Xilinx FPGA, FLASH EEPROM, FiberChannel transceiver, as well as RS422, RS485 and ECL interfaces.

Helped test newly manufactured boards for a different program.

September 2002 to

February 2003

Contract engineer at Unitec Electronics, Jessup, Maryland. Responsibilities:

Designed and tested two boards for Unitec's next generation carwash entry system. One was the interface board between the system CPU and a number of other devices such as thermal printer, proximity detector, TFT LCD display, shock sensor, keypad, mouse and keyboard, siren, magnetic card reader, RFID reader, ... . It also had two DC/CD converter circuits and a stereo audio amplifier circuit. The second board was a relay board that interfaced to the carwash system to control different operation cycles.

November 2000 to

February 2002

Contract engineer at Internet Photonics, Inc. Shrewsbury, NJ (a Lucent Technologies spin-off), Responsibilities:

Designed an MPC860 microcontroller board with Flash, SDRAM, FPGA, 10/100Mbps Ethernet, ... as a general-purpose controller board.

Designed portions of an FPGA used on an optical board. Functions implemented included I2C bus interface, EEPROM interface, and other control/glue logic. Also, captured the schematic for the complete board and another optical board with similar functions.

Reviewed the design of a PowerPC405GP board and compiled design verification test document for the board.

July 2000 to

November 2000

Contract engineer at Lucent Technologies, Holmdel, New Jersey. Responsibilities:

Trouble shot an existing 10 Gigabit/Second SERDES board. Designed a new version of the board (under supervision of more senior engineers) using an Altera FPGA, a 16X1 SERDES chip and other components. Also, designed the internal FPGA circuitry.

September 1999 to

December 1999

Contract engineer at Tellabs Corporation, Hawthorne, New York. Responsibilities:

Helped test the "Main Administrative Module" of Tellabs TITAN 6100 Optical Transport System (OTS). The board was a combination of a mother board and a daughter board. The daughter board had four MPC860 systems and a number of Ethernet LANs. The mother board had more Ethernet LANs and power supply. Both boards had XILINX FPGAs.

Compiled a high level design document for that board.

June 1997 to

April 1999

Contract engineer at Telephonics Corp., Farmingdale, New York. Responsibilities:

Designed various digital boards and FPGAs for different applications such as control panels and interface circuitry to military encryption devices.

Wrote documentation for above designs.

Work Experience: Full-time positions

September 1996 to

April 1997

Hardware/Software engineer at InterDigital Communication Corporation, Melville, New York. Responsibilities:

Reviewed and tested an MC68360 microcontroller board. The board included several FPGA and EPLDs as well as 6 identical daughter boards.

Simulated, tested and modified two of the FPGA designs. Wrote test routines in C and assembly.

Wrote automatic test routines for production testing of the board.

October 1994 to

September 1996

Design engineer at Telephonics Corporation, Huntington, New York. Responsibilities:

Designed an FPGA to provide serial interface between an I8088 processor board and a switch panel. The switch panel included push-button, rotary and toggle switches as well as numerous indicator LEDs.

Designed an FPGA to provide serial interface between an I8088 processor board and an analog board. The analog board used digitally controlled DAC 8840's and analog switches.

Designed FPGAs for test fixtures and other applications.

July 1992 to

October 1994

Design engineer at Smar Research Corporation, Ronkonkoma, New York. Responsibilities:

Designed a family of digital communication controllers. These ICs implement the digital portion of the physical layer of Fieldbus communication standard. Each IC included a Manchester transmitter and receiver as well as microprocessor glue logic. The later members of the family provided memory management and DMA control logic.

Designed a digital switch and Fieldbus line arbitrator. This IC monitors two Fieldbus lines and outputs the first active line.

Interfaced above ICs to an HC11 microcontroller system and developed software for the system to transmit and receive on a Fieldbus line.

Designed an FSK transmitter and receiver based on Bell-202 standard.

Wrote data books and application notes for above ICs.

November 1991 to

April 1992

C programmer at ColorCode Unlimited Corporation, Newton, Massachusetts. Responsibilities:

Created a demo program that partially demonstrates ColorCode's ideas. It involved computer graphics, text processing and encryption.

Put together an artificial vision system using a PC, a CCD camera, an image processing board and a TV set. Also programmed the system to capture images and store them in a file.


Furnished upon request.

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