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Design Engineer Test Cases

Location:
Hyderabad, Telangana, India
Salary:
450000
Posted:
January 09, 2018

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Resume:

SAITEJA CHILOJI

Design Engineer

Mobile: +91-949******* Email: ac3yli@r.postjobfree.com

OBJECTIVE

Aspiring design engineer with an attitude to seek challenges for bench marking designs in FPGA’s and consistantly work as a team towards the organizational objectives

TECHNICAL SKILL SET

HDLs : Verilog, Vhdl(basic)

HVL&Methodology : System verilog, UVM(basics)

Programming Languages : C, TCL

Platforms : Windows, Linux(basic)

Simulators : Modelsim, Questasim, isim

FPGA Tools : Xilinx ISE, Xilinx Vivado, EDK&SDK

FPGAs : Zedboard, Vertex-5, Kintex-7

TRAINING & EXPERIENCE

PMI Pvt. Ltd - Hyderabad

Design Engineer Sept-2017 to Present

Implementation of RTL code for Custom boards

Execution of White box & Block box testing

Implementing test cases

Execution of ATP

Sandeepani School of VLSI Design - Bangalore

Trainee VLSI Design & Verification Dec-2016 to June-2017

Completed Professional Development Course ( PDC ) in VLSI Design &Verification(Front-end)

ACADEMIC PROFILE

Course

Institution

University / Board

Aggregate Percentage

Batch

B.Tech (ECE)

Lovely Professional University

Lovely Professional University

6.32 CGPA

2016

HSC

Narayana Junior College, Hyderabad

Board of Intermediate Education, A. P.

93.7

2012

SSC

SRR High School, Jannaram

Board of Secondary Education, A.P.

84

2010

INTERNSHIPS & WORKSHOPS

Attended three days training program on “CCNA & Ethical Hacking” at Jetking Solutions,

Jalandhar

Attended six week training on “ LabVIEW ” at SV Consultants and Technologies,

Hyderabad

PROJECTS

Major :

Design and functional verification of AMBA bus protocol(AHB to APB Bridge) using Sysytemverilog

The AHB to APB Bridge, sub blocks of AMBA model has been designed using SystemVeriog and verified for functionality using QuestaSim. The FSM of all the three blocks are modelled and synthesized using Xilinx Vivado. The sub blocks are integrated to create the top module and verified for functionality. The BFM of the master & slave has been developed using SV and verified for functionality

Design and functional verification of Frame Detector for HDLC Controller

HDLC is a bit oriented code transparent synchronous data link layer protocol developed by

ISO. The framer defined has 60 bits frame size which has three headers which is 4 bits(1010)

with 16 bits payload(total 20 bits). The framer module has been simulated using QuestaSim.

The design has been synthesized and implemented on Kintex -7 FPGA and working at a

Frequency of 200MHz

Academic:

B.tech Project: Design and functional verification of UART module

The UART is modelled using Verilog and verified for functionality. The sub blocks are integrated to create the top level module. The design has been synthesized and implemented for Spartan-6 and design is working at a frequency of 400MHz

Minor:

Memory Modeling and Verification

Single port BRAM(Block RAM), single port DRAM(Distributed RAM), ROM with synchronous read, ROM with asynchronous read, and Dual port memory architectures are modelled in Verilog and verified for functionality using Questasim

Design and FPGA implementation of fuzzy logic based PID Controller

This project deals with the design of fuzzy logic based PID controller which will automatically control the speed of vehicle either by increasing or decreasing. The cruising system with fuzzy concept has been developed to avoid the collision between the vehicle and road. The code was synthesized and implemented on Kintex-7

ACHIEVEMENTS

Best Drummer in Battle of Bands, 2015

Lowest time record in solving Rubik’s Cube (42secs)

Second prize- Jawahar Science talent test, 2010

PERSONAL STRENGTHS

Team player & Co-ordinate among the team members

Eager to learn new technologies and work with interest

Adaptable, Flexible, Optimistic

DECLARATION

I do hereby confirm that the information given above is true and to the best of my knowledge

SAITEJA CHILOJI



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