VLADIMIR B ZAKLADNYI

**** ****** **, *** ****, CA, 95124 408-***-**** ac3e2k@r.postjobfree.com

EXPERIENCE SUMMARY:

Proficient C/C++ software development;

Multi-threading, STL, TCL, Perl, Linux/Unix/Windows;

EDA/CAD, Global & Detail & ECO routing, VLSI/ASIC/FPGA designs;

DRC/LVS physical layout verification;

GUI development, Routing Editor, Motif, Qt.

-Development of algorithms and implementation for Block & Chip-level routing.

-Routing flow for advanced technologies (TSMC_16/10/7nm, Samsung_14/10nm) consisted of consequent iterations of library preparation, global routing and detail routing stages.

-Library cells preparation for detail placement validation, timing/EM library characterization, better and faster routing flow convergence.

-Initial and incremental global routing.

-Detail routing, timing driven ECO routing, SI repair.

-Double/Triple Patterning.

-Layout geometry computation for DRC/LVS violations prevent and verification.

-Dynamic and post-route DRC/LVS verification.

-Calibre LFD and Calibre InRoute driven routing correction, DFM optimization.

All projects were developed from scratch and delivered to customer.

EMPLOYMENT HISTORY:

Principal Technologist

Mentor Graphics Corp. Jun 2007 – Jul 2017

Projects: Olympus’s Global & Detail & ECO routing; Library preparation;

DFM optimization for advanced technologies (28nm to 7nm); DRC/LVS verification.

Senior Member of Technical Staff

Sierra Design Automation, Inc. Jul 2005 – Jun 2007

Projects: Olympus’s Detail & ECO routing for (65nm to 32nm); DRC/LVS verification.

(acquired by Mentor Graphics)

Senior Staff Software Engineer

Golden Gate Technology, Inc. Nov 2001 – Jul 2005

Projects: Global & Detail routing, DRC/LVS verification & cleanup; custom structured design routing.

Senior Staff Engineer

Synopsys, Inc. May 2000 – Nov 2001

Projects: RouteCompiler’s Global & Detail & ECO routing; GUI routing editor.

Senior Software Engineer

Gambit Automated Design, Inc. Sep 1993 – May 2000

Projects: Global & Detail routing, GUI floorplan & routing editor.

(acquired by Synopsys)

PATENT:

US 7260804 B1 - Method for circuit block routing based on switching activity

EDUCATION BACKGROUND:

Moscow Technological University

Master’s degree, Computer Engineering

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