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Memory Design Engineer

Location:
Bengaluru, Karnataka, India
Posted:
January 30, 2018

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SHARATH B.P

BSK *rd stage, Kattriguppe,

Bhuvaneshwari Nagara India, Email id: ac39c6@r.postjobfree.com Karnataka, Bangalore-560085 Contact No: 984-***-**** CARRIER OBJECTIVE:

To achieve a dynamic and challenging role in the area of engineering and domains that will offer the best opportunity to enhance my ability and skills and to make carrier being efficient. TECHNICAL EXPERIENCE:

Having 2.7 years of experience as Memory design Engineer, this includes 1.7years (June-2016 till date) of experience at ARM Embedded Technologies and 1year of Internship experience.

Knowledge on ROM, SRAM and RF single port memories.

Basic Understanding of different Memory architecture and signal flow in the architecture.

Bitcell extraction and Iread analysis.

Worked on Bitcell analysis of 6T SRAM cell.

As a part of pre-sales team involved in understanding the customer needs and specifications and provided the competitive timing data to the customer.

Basic knowledge of other memories such as content addressable memories (CAM) and Flash Memory.

Presented various technical papers in International Conference, National conference and IEEE conference.

EDUCATION QUALIFICATION:

Vellore Institute of Technology (VIT) University, India, Tamilnadu May 2016 Master of Technology (MTECH) in VLSI Designs 8.37(cgpa) Visveswaraya Technological University, India (APSCE) Bangalore August 2013 Bachelor of Engineering (BE), Telecommunication 63% TECHNICAL SKILLS

EDA Tools & Simulators : Cadence tools: Virtuoso Schematic Editor, Spectre simulator. Mentor Graphics: Pyxis schematic Editor, ELDO spice, PERC, CalibreXRC Synopsys : Hspice, StarRc

Xilinx ISE

Scripting : Shell Scripting

RELOCATION: I am happy to re-locate if the situation warrants it. PROFESSIONAL EXPERIENCE Jun-2016(Till date)

Currently working as a Design Engineer at ARM Embedded Technologies Pvt Ltd as Consultant. PROJECTS:

1) SMIC – 28nm

Circuit check analysis at schematic level which includes ERC checks using caliber Perc, Dynamic Checks and DC path checks for ROM compiler.

Setting the read margin limits for ROM compiler which involves the analysis of read critical path.

Setting up the internal flow for leakage and analysis is done for various leakage modes and checking the trend across different modes for RF and ROM compiler.

Sense amplifier offset analysis for RF compiler.

Front end verifications for both RF and ROM compiler. 2) UMC – 40nm

Taking the full ownership for the re-release of SRAM compiler.

Re-release was done after the leakage fix by removing unwanted devices for power gating off instances.

All the front end verifications was done and released to the customer. 3) PreSales Team

As a part of presales team worked for foundries such as GF, UMC and TSMC for various technology nodes.

Projecting the timing data for GF-14nm and TSMC-28nm as per the customer requirement.

Bitcell analysis for UMC-40nm.

Read and write margin analysis.

Memory Design and Characterization

Internship at 3D-IP Semiconductor Pvt.ltd Aug-2015 to Jun-2016

Part of a custom IC design group currently responsible for the development of ROM memory in 28nm technology from scratch.

Responsible for the schematic design of leaf cells, sense amplifier and the local control block.

Responsible for the design of wordline strap cells.

Analysis of the self-timing path design

Timing analysis such as access time, address setup and hold time, cycle time is done across PVT’s.

Writing measure and stimulus for memory timing characterization.

Basic understanding of timing marginalities.

MTECH PROJECTS

Project: The design of 16X8 SRAM

Description:

Aim of the project is to study about 6T based SRAM and to design a 16X8 SRAM on CADENCE tool.

Designed a 16X8 SRAM with all associative circuitry such as precharge circuit, column decoder, Row decoder, Column mux, write driver and sense amplifier using TSMC 45nm technology.

Design was done using the cadence virtuoso and timing characterization is done across PVT’s using HSPICE.

Project: The Design of Memristor based Content addressable Memory (CAM) for high speed, low power search applications.

Description:

Aim of the project is to study about the different types of CAM cells.

Designed different types of CAM cells such as NAND CAM, NOR CAM and XOR CAM cells using CMOS and Memristor.

Analysis of power consumption for both CMOS and Memristor based CAM cells.

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BE PROJECT: INTERNSHIP Oct 2012 – Mar 2013

Project: Power Gating to reduce Leakage Current in Low Power CMOS Circuits was carried at Next Generation Institute of Technology.

Description:

Aim of the project is to reduce the leakage current in Nanometer CMOS circuits by a radical new technique of insertion of sleep transistor to a cell/block.

Emulated the working of a chip by designing counters, adders and multipliers in single block/cell using 45nm technology in CADENCE tool and simulation is done using HSPICE.

Basic understanding of different types of power gating techniques. AREAS OF INTEREST

Memory Design, Mixed signal design and Physical design. IEEE PUBLICATION

Published a paper titled “The Design of Memristor based Content addressable Memory (CAM) for high speed, low power search applications” as the paper is recently accepted yet to publish in IEEE digital Xplore.

INTERNATIONAL PAPER PUBLICATIONS

Published a paper titled “Power gating to reduce leakage current in Low Power CMOS circuits” in International Organization of Scientific research – Journal of VLSI and Signal processing(IOSR-JVSP), volume 3, issue 3.

Published a paper titled “A New Approach to the design and Implementation of Multipliers using Reversible Logic” in International Journal of Engineering and Science Invention (IJESI) and indexed in American National Engineering Database(ANED) with a digital data link(DDL) number 26.6718/021********

NATIONAL CONFERENCE PAPERS

Presented a paper titled “Power gating to reduce leakage current in Low Power CMOS circuits” in the National Conference held at Jyothi Institute of Technology, ETET-2013.

Presented a paper titled “A New Approach to the design and Implementation of Multipliers using Reversible Logic” in National Conference held at AMC college of Engineering, VCCN-1.

Presented a paper titled “Ultra low Power 14XM Fin FET’s Process – A Radical New Approach of Transistor” in the National Conference held at AMC college of Engineering, VCCN-1. DECLARATION

I hereby declare that information given by me is true to best of my knowledge and belief. SHARATH B.P



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