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Project Design

Location:
Bengaluru, Karnataka, India
Posted:
January 19, 2018

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Resume:

V.P.Sampath

ac33k8@r.postjobfree.com

Cell: +919*********

EXPERIENCE SUMMARY: OVERALL EXPERIENCE 13 YEARS

* *************** ** ***/**** DESIGN

* ***** ********** ** **** DESIGN

Summary

FPGA Prototyping using Xilinx-Virtex-7, Zynq, Spartan6, Spartan3 and in test equipment’s.

Work with design, design verification, and FPGA teams to compile, download and test FPGA bit streams.

FPGA board bring up and firmware development.

Ensure that the firmware developed can be utilized for RTL simulations.

Debugs FPGA software products, including Driver, through the use of systematic tests to develop, apply, and maintain quality standards for company products.

Exposed to ARM SoC boards.

Exposed to networking protocols and DSP.

Execute test cases for hardware software integration.

Exposure to shell, TCL.Familiarity with the GNU tool chain and Linux.

Designed, developed wireless communications FPGA code for existing client products.

Exposure to audio amplifier. Knowledge of Perl and C programming.

Knowledge of communication protocols (I2C, SPI, UART, USB, LIN, CAN, FLEXRAY) and AXI protocols.

Exposure in PSPICE, ORCAD, PCB Design.

Interact with various vendors, customers and component manufacturers for product design.

Co-ordinates with and supports contract manufacturers and production department in creating prototypes.

Mentoring team, Writing articles in Electronics for You, IEEE Newsletters.

Technical Summary

RTL design, Timing/Area optimization for FPGAs.

Digital filter implementations (FIR/IIR) and other hardware optimization for algorithms in FPGA.

Knowledge in ASIC flow using Cadence, Timing analysis for logic designs.

Skills

H/W Languages : VHDL, Verilog, for design

Software/Scripting: TCL Unix shell, Matlab & Simulink

Bus/Interfaces : Gigabit Ethernet, I2S, I2C, SPI, UART, RTC, DSP Interfaces, Microprocessor, and

peripheral Interfaces

FPGA : FPGA Synthesis, FPGA Board Bringup, FPGA Debugging

Board Design : PCB Design

Tool Expertise

Simulation:NCSim, Modelsim, Xilinx ISim,Questasim

Design : Xilinx Vivado, ISE, SDK, Altera Quartus

Debug : Xilinx ChipScope Pro, Spectrum Analyzer, Oscilloscopes

DSP :Matlab Simulink, Xilinx System Generator,

Professional Experience:

Technical Architect,SiValley Technologies Dec 2017-Till date

Technical Architect, Adeptchips Feb 2017-Dec 2017

Project Officer, NIELIT March 2013-Jan 2017

Design Engineer, Ram Innovation Labs Oct 2008 – Feb 2013

Team Member,Telesoft Neutek, June 2008-Oct 2008

Freelancer- Ilakshya Private Limited Jul 2007 - Jun 2008

Project Engineer, Leela Scottish Private Limited Jun 2004 – Jul 2005

Electrical Engineer, The Builders May 2001- June 2004

Adeptchips, Technical Architect

Project 1:Flexray Protocol

Role : RTL of Flexray transmitter and RTL Integration

Skill/Tool:Questasim,VIVADO 2015.4

Tools

VIVADO

Simulator

ISIM

Debugging

Chipscope Pro

Platform

Xilinx Virtex 7 Development kit

The RTL of the Flexray transmitter was done and simulated. The Flexray transmitter and receiver modules are integrated with the APB Slave and validated on the Virtex7 FPGA Board.

Period: 1 month

Project 2: CAN Protocol

Role : RTL of CAN transmitter and RTL Integration

Skill/Tool: Questasim, VIVADO 2015.4

Tools

VIVADO

Simulator

ISIM

Debugging

Chipscope Pro

Platform

Xilinx Virtex 7 Development kit

The RTL of the CAN transmitter was done and simulated. The transmitter and receiver modules are integrated with the APB Slave and validated on the Virtex7 FPGA Board.

Period: 1 month

Project 3: LIN Protocol

Role : RTL of LIN protocol and RTL Integration

Skill/Tool:Questasim, VIVADO 2015.4

Tools

VIVADO

Simulator

ISIM

Debugging

Chipscope Pro

Platform

Xilinx Virtex 7 Development kit

The RTL of the LIN Protocol core was done and simulated. The LIN Controller module are integrated and validated on the Virtex7 FPGA Board.

Period: 1 month

Project 4 : USB 3.0 IP Validation in FPGA

Role : RTL Integration and RTL Validation on FPGA

Skill/Tool: VIVADO 2015.4

Tools

VIVADO

Simulator

ncsim

Debugging

Chipscope Pro

Platform

Xilinx Virtex 7 Development kit

USB3.0 core is validated on VC707.USB 3.0 core was integrated and validated in Virtex 7 (VC707) through the GTX Transceiver with a data rate of 10 Gbps.

Responsibilities: Targeted for Xilinx FPGAs and validation

Period 6 months

NIELIT Chennai, Project Officer

Worked as platform development for the Automotive domain by investing on ASIC and FPGA Technologies.

Project 5: FPGA based Multi-vehicle bus controller

Role : RTL design and FPGA Synthesis

Skill/Tool: VIVADO 2015.4

Tools

VIVADO

Debugging Tool

Chipscope pro

Platform

Xilinx Virtex 7 Development kit

Description:

The project focused on the design of the frame transceiver of MVBC. It is mainly responsible for the transmitting and receiving of the frame. The design module of the Manchester encoding/decoding, CRC generation and checking for the MVBC is done.MVBC is connected with MVB via a dual redundant provided by the physical layer and receives CPU Access control in order to get and send device in MVB.

Responsibility:

Responsible for requirement understanding.

FPGA architecture development.

Work schedule, resource estimation.

RTL design based on Verilog.

RTL implementation targeted for Xilinx FPGAs and validation.

Challenges faced:

The main challenge of the system in which the system generates MVB frames transmit through the bus and the frames received in response. The transmission of data packets and analyze a variety of errors of the received data frame. The fixing of the errors is done at the received data frame.

Period 1 year

Project 6: CDMA Scheduler Implementation

Role : RTL design and FPGA Synthesis

Skill/Tool : VIVADO 2015.4

Tools

VIVADO

Debugging Tool

Chipscope Pro

Platform

Xilinx Virtex 7 Development kit

Technology

CDMA

Description

The project involves the complete design from requirement to standalone device. The generation of orthogonal variable spreading Factor (OVSF) codes was done. The system in which the generated Bus Arbiter acts as an interface between the transmitter and the receiver. The token bit is rotated left each cycle and the token is initialized to the reset phase.

Responsibility:

To design and verify the functionality of the CDMA Scheduler.

Responsible for requirement understanding, FPGA architecture development

Work schedule, resource estimation, RTL design based on Verilog, RTL implementation targeted for Xilinx FPGAs and validation

Challenges faced:

The main challenge of the system in which the generated Bus Arbiter as an interface between the transmitter and the receiver where the data packets scheduled time is not met. It employs token concept from a token ring in a network. The acknowledge signal to the bus arbiter is delayed by one arbitration cycle.

Period 6 months

Project 7: FREE RTOS PORTING ON ZED FPGA

Role : Free RTOS Porting and along with the Xilinx SDK to add networking Capability to an embedded system.

Skill/Tool: VIVADO 2015.4

Tools

VIVADO

Platform

ZED 7020

Description:

Free RTOS Application and BSP using Xilinx SDK.TFTP server.TCP RX throughput test.TCP TX throughput test.

Responsibility:

RTOS Porting

Period 3 months

Project 8: FPGA IMPLEMENTATION OF UART IN ZED BOARD

Role : RTL design and FPGA Synthesis

Skill/Tool: VIVADO 2015.4

Tools

VIVADO

Platform

ZED 7020

Description:

The creation of the processor system using Vivado tool. The UART was implemented on ZED board and using Petalinux. We booted the Linux on Zedboard.It involves board bring up activity

Responsibility:

.

To implement the UART on ZED board and test the hardware

Firmware development and debugging.

Challenges faced:

The main Challenge is the UART implementation on ZED board and using Petalinux on a build machine and Linux Build for ZED board and to test in the hardware. Building the boot system by building U-Boot,Linux Kernel and gen FSBL using SDK and creating boot.bin by combining FSBL with U-Boot

Period 2 months

Ram Innovation Labs, Design Engineer

Project 9: FPGA Based OLED Display by SPI interface

Role : RTL design and FPGA Synthesis

Skill/Tool: Xilinx ISE 14.2

Tool

Xilinx ISE 14.2

Platform

Spartan6

Description:

Xilinx FPGA is used in this work and block RAM can be configured as a memory with different data widths and depths.OLED Display was implemented in the FPGA. We are able to display any sort of graphical design by programming the device through SPI as well as sending bitmap images.

Responsibility:

To implement the OLED Display on FPGA board and test the hardware.

FPGA debugging.

Challenges faced:

The main Challenge of the system is to flash the OLED through SPI interface. The display of the numerical and the customized display is implemented in the same.

Period 4 months

Project 10: Development of Special Coding Techniques To Compress Video Data

Role : RTL design and FPGA Synthesis

Skill/Tool : XILINX ISE 14.2

Tool

Xilinx ISE 14.2

Platform

Spartan6

Description

The design is of achieving loseless compression. The demand for establishing the data compression is applied to image data. At each level of de-composition, the LL sub-band from the previous level is decomposed using a 2-D -DWT & thus is replaced with 4 new sub-bands.

Responsibility:

To implement the DWT on FPGA board and test the hardware.

Challenges faced:

The main Challenge of the system is to compress the data is with the 3-level, 2-d separable DWT by de-correlation which has 9 taps for LPF and 7 taps for HPF

Period 1 year

Project 11: FPGA Based Intrusion Detection

Role : RTL design and FPGA Synthesis

Skill/Tool : VIVADO

Tool

Xilinx ISE 14.2

Platform

Spartan6

Description:

The project involves complete design from requirement to standalone device.The first block of the TCP/IP data is fed into the input state machine which splits into a header and a payload part.The design unit involving two 32- bit adders and one 16 -bit adder. The Memory gateway takes the payload data and writes it to the appropriate position in its 32-bit wide memory. The Xilinx FPGA is used in this work and one such block Select RAM can be configured as a memory with different data widths and depths. It involves the RTL Design and FPGA Synthesis

Responsibility:

To implement the Intrusion based system on FPGA board and test the hardware.

Firmware development and debugging.

Period 1 year

Project 12: CDMA Transmitter

Role : RTL design and FPGA Synthesis

Skill/Tool : VIVADO

Tool

Xilinx ISE 14.2

Platform

Spartan6

Technology

CDMA

Description:

The systems consist of an uplink transmitter and receiver developed upon the basis of wideband code division multiple access (WCDMA) technology. WCDMA is widely accepted 3G interface based on direct sequence (DS) CDMA technology. System clock is applied to FIR and modulation block.Project involves RTL and implementing in FPGA

Responsibility:

To implement the uplink transmitter and receiver on FPGA board and test the hardware

Firmware development and debugging.

Challenges faced:

The main challenge of the system is to develop aa prototype for an uplink CDMA System

Period 1 year

Project 13: Audio receiver

Worked for developing internet radio receiver patent.

Co-curricular Activities:

Editorial letters in the leading newspapers and in the Hindu Opportunities

Columns appeared in the IEEE Institute, September 2012., IEEE India Council Letters, IEEE MAS sections, IEEE India Newsletters

Contributions to Electronics For You (EFY) as follows:

FPGAs for The Internet of Things dated AUGUST 2015 EFY magazine

FPGA Prototyping Techniques dated DECEMBER 2015 EFY magazine

GATE LEVEL SIMULATIONS: An Increasing Trend dated FEBRUARY 2016 EFY magazine

How Cloud Based RADIO ACCESS NETWORKS Can Solve Operators ‘Problems MAY 2016

VEHICLES ‘ETHERNET Emerging Trends and Challenges JULY2016 EFY magazine

FAST-TRACK EVALUATION AND PROTOTYPING dated OCTOBER 2016 EFY magazine

7nm IC Technology Trends and Challenges Part 1 DECEMBER 2016 EFY magazine

7nm IC Technology Trends and Challenges Part 2 JANUARY 2017 EFY magazine

Hybrid Emulation Trends and Challenges APRIL 2017 EFY magazine

Self-Driving Cars Trends and Challenges Part1 MAY 2017 EFY magazine

Self-Driving Cars Trends and Challenges Part2 MAY 2017 EFY magazine

Heterogeneous Architectures JULY 2017 EFY

FPGA in Datacenters-Opportunities and Challenges AUGUST, SEPTEMBER EFY

Convolutional Neural Networks for Autonomous Cars OCTOBER EFY

INTERNATIONAL CONFERENCES:

Accepted:

●“FPGA Based System For Multi-Vehicle Bus Controller”

V. P. Sampath, V. Kasivishwanathan 2014 International Conference on e-Learning, e-Business, Enterprise Information Systems, and e-Government, World Congress of Engineering

●“Smart and efficient onboard image compression using reconfigurable Hardware” has been accepted for the IEEE-International Conference on Emerging Trends in Science, Engineering, Business and Disaster Management- ICBDM 2014 on 28th February, 2014 at Noorul Islam University, Kanyakumari.

●“Image Compression For Space Onboard Remote Sensing” 17th International Conference on Image Processing, Computer Vision, & Pattern Recognition July 22-25, 2013, Las Vegas, USA.

●“A Generic Architecture for on chip CDMA based switch” at Euro micron Conference at Germany, May 2007.

Membership Activities

Senior Member, IEEE

Member, Institution of Engineers

IAENG Membership

Reviewer for IJERT Journal



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