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Engineer Manager

McKinney, Texas, United States
November 12, 2017

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Peter T Nguyen

**** ******** ****** *****

McKinney, TX 75070

214-***-**** (m) ;


To secure a challenging Marketing/Product/Program Management position with growth potential.


Methodical, self-initiated, self-motivated, and hardworking manager with over 20 years of diverse experience from design to marketing in various industries, extensively communication. Proactive team player with vision, character, and dedication to success.

Proven track record in generating business with large global customers and distributors. Demonstrated ability to identify and launch a new product to a new market segments with a well-defined plan of actions and an entrepreneurial orientation.

Ability to make quick decisions, to lead, to organize, and to manage projects after careful risk analysis. Ability to develop strategic relationships internally and externally and sell the vision. Ability to influence at multiple levels of an organization. Ability to learn and analyze complex technology quickly.


ITIL v3 Foundation, Continuous Service Improvement (CSI), Planning/Protection/Optimization certificates (PPO). In depth experience in all phases of ITIL stages: Service Strategy, Service Design, Service Transition, Service Operation, and Continuous Service Improvement including all functions and tasks under IT Service Management, IT Business Management, IT Operations Management, Application Management, and Security which are provided under tool sets such as company proprietary or Servicenow.

Extensive and successful track record of leading a product portfolio, with P&L (profit and loss) responsibility, in a high-tech global environment, for a sustained period of time of at least 5 years of post- production.

Extensive experience in generating business development/proposal/case including market analysis, competitive analysis, pricing and cost analysis, constructing and presenting market positioning, marketing and product collateral materials to multiple departments at customer visits, participating in trade shows, demos, and special venues with executive management, marketing, Research and Development, supply management, transition management, and Application Managed Services (AMS).

Extensive experience in understanding customers’ needs and requirements, finding key contacts in different departments and finding key decision making personnel at early stage for near term and future programs.

Extensive experience in requirement gathering, Q/A, project scheduling and development supervising (hardware, software, operation, test, manufacturing), Request For Proposals (RFP), and Request For Quotation (RFQ).

Technical Skills: Windows, OS, Sonar, Radar, Optical (OC 3/12/48/192), multiple physical layer types, ATM QoS (ABR, CBR, VBR, etc ABR video ecosystems including encoding, packaging and ad/program substitution, MPLS, PIP, Private Line, Ethernet, Video, Conferencing, Voice, Cloud, SaaS, IaaS, SONET/SDH (BLSR/UPSR), PDH, Fiber Channel), FR/ATM, Enterprise Network, SNMP Network Management (TL1), Ethernet over SONET/SDH or PDH, and Microsoft tools. Familiar with C/C++, IP, IP over SONET, IP over ATM, Wireless technologies, ATCA/µTCA, ICON, BGW, MECCA, XNG, TCOMS, GRIP, and nSAP.


Genpact, Richardson TX 09/17 – Present

Front Line Manager

Managing team of over 20 processing agents responsible for assisting our community and help resolve inquiries empathetically, accurately and on time; becoming and remaining knowledgeable about client’s products and community standards; making well balanced decisions and personally driven to be an effective advocate for our community; demonstrating strong interpersonal skills, verbal and written communication skills and most importantly empathy; displaying a strong bias to doing what’s right for our community in supporting the client’s mission; investigating and resolving issues that are reported on clients site such as requests for account support and reports of potentially abusive content; responding to user inquiries with high quality, speed, empathy and accuracy; using market specific knowledge, signals and insights to spot and scope scalable solutions to improve the support of our community of users; gathering, analyzing and utilizing relevant data to develop ways to improve the overall user experience on the site; enforcing client’s Terms of Use by carefully monitoring reports of abuse on the site; reviewing the reported content within agreed turnaround times and standards of quality; identifying inefficiencies in workflows and suggest solutions; and recognizing trends and patterns, and escalate issues outside the company policy to the global team. Managing responsibilities also include productivity and accuracy per client’s SLA and KPI, performance improvement plans, workload distribution, scheduling, and cohesiveness.

Southern Methodist University, Dallas TX 07/17 – Present

Adjunct Professor

Teaching graduate engineering courses in Telecommunication, Optical and DWDM networks including Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), Optical Transport Network (OTN), Optical core, access network configurations, Wavelength Division Multiplexing (WDM) network elements and control and management of optical networks, overview of network survivability using optical technologies. Future optical technologies including 100G, 400G, and photonic packet switching are also covered.

Verizon Enterprise Solutions, Richardson TX 05/11 – 03/17

Technical Program Manager

Providing technical support for customer accounts with annual revenue of at least $10M. Services include but not limited to voice, data/Internet, video, UC&C, cloud, and wireless. Responsibilities include but not limited to proactive focus on account, customer meetings and presentation, contract SLA management (MTTR, availability), KPI monitoring, network optimization reviews, network hardening and enhancements, incident reports, maintenance evaluation and communication, customer entitlements, and service improvement plans.

Providing product management support for multiple market and application segments such as banks (Bank of America and Wells Fargo), airlines (American Airline), and manufactures. Performing launching and implementation of new services, developing business strategy to enhance revenues, providing daily client relationship management, maintaining internal business and external customer relationships, gathering customer requirements, making recommendations to customers on network enhancement including backup and recovery strategies, and presenting validity justification to business units with concrete scenario and roadmap.

THV Enterprise, Dallas/Fort Worth TX 11/08 – 05/11

Program/Product Managing Consultant

Providing consultant services to a communication Integrated Circuit (IC) manufacturer on analyzing future product roadmap and offerings in their communication product line for PDH, SDH/SONET, Carrier Ethernet, and OTN. Services include business development/proposal/case, ROI, strategic marketing, product planning, market analysis, product distribution evaluation, pricing analysis, competitive study, and product cost analysis.

Enfora Inc., Richardson, TX 04/08 – 10/08

Sr. Product Line Manager

Responsible for product line management of wireless mobile tracking product family for Telematics M2M markets including asset tracking that is recognized as the value and performance product leader for the “field and forget” asset tracking segment and mobile tracking to provide diagnostic solutions especially targeted at fleet trucking and heavy equipment. Wireless technologies supported include but not limited to quad-band GSM/GPRS, GPS, and Satellite. Responsible for business case, ROI, RFQ/RFP, P&L, strategic marketing, product planning, market analysis, product distribution evaluation, pricing, promotion analysis, competitive study, feasibility study, product literatures, customer feedbacks, product cost analysis, and product delivery.

Maxim Integrated Products, Dallas, TX 05/02 – 01/08

Strategic Marketing Manager – Communication and Synchronization Product Lines

Responsible for business case, ROI, RFQ/RFP, P&L, strategic marketing, product planning, market analysis, product distribution evaluation, pricing, promotion analysis, competitive study, feasibility study, product literatures, customer feedbacks, product cost analysis, and product delivery. Design related responsibilities include managing product life cycle and supervising R&D (system engineering, design engineering, field application engineering, and application engineering) for the entire end-to-end product design cycle.

Highest achievements in the business unit:

Expanded T3/E3 product line from 2 products to more than 14 products and from few $K to excess of $10M annual revenue in 3 years with average annual gross profit of at least 60%.

Multi-Channel (1/2/3/4) DS3/E3 ATM/Packet PHY with/without LIUs product – Performance results: Team of 18 engineers (4 system and 14 design); Excess of 3M (0.35 m) transistors; 27mm 400-lead CSBGA (1.27mm); 12-month design cycle (launch to introduction); 1st revision (A1) success for product introduction – 1st and most successful product ever in the business unit; Estimate 10-year life time revenue of >$90M with average of 75% Gross Profit Margin (GPM); more than 20 customer champions including Cisco, Nortel, Lucent, and Alcatel.

Higher density (6/8/12-port) DS3/E3 ATM/Packet PHY without LIUs products – Performance results: Excess of 9M (0.18 m) transistors, 27mm 676-lead CSBGA (1mm); 9-month design cycle (launch to introduction); Estimate 10-year life time revenue of >$18M with average of 80% Gross Profit Margin (GPM); more than 5 customer champions including Cisco, Nortel, Juniper, and Rad Communication.

Product portfolio includes:

Ethernet Over SONET/SDH (EoS) and Ethernet Over PDH (EoP): Pin compatible, software compatible, multi-channel (8 T1/E1, 8 T3/E3, 32 TDM, 2 PCM, 8 10/100-Mbps and 1 1000-Mbps Ethernet) with integrated T1/E1/T3/E3 framers, E/FE/GBe MACs, EoS/EoP mappers, High Order and Low Order Virtual Concatenation (HO/LO VCAT), Link Access Protocol Over SDH (LPAS), Link Capacity Adjustment Scheme (LCAS), up to 250ms differential delay, flexible and intelligent traffic management, Q-in-Q/cHDLC engines, and HO/LO SONET/SDH mappers (STS-1/VC3/VC4/VT1.5/VC11, VT2/VC12).

Next generation clock synchronization products supporting all traditional frequencies for TDM networks (SONET/SDH and PDH), packet (Ethernet), and new standard IEEE 1588 time synchronization.

T3/E3/STS-1 (45/34/52-Mbps) Line Interface Unit (LIU) devices: Pin compatible, software compatible, multi-channel (1/2/3/4/6/8/12) devices with jitter attenuation, clock adapter, and desynchronization FIFO. All devices meet Bellcore Telcordia, ANSI, and ITU T3 and E3 jitter compliant including jitter generation, jitter transfer, and jitter tolerance.

T3/E3/STS-1 Unchannelized, pin compatible, software compatible, multi-channel (1/2/3/4/6/8/12) devices: standalone framers, ATM/Packet PHYs with embedded framers with/without embedded LIUs, and SONET/SDH OC-3/12 mapper with/without embedded LIUs. All products are in production.

White Rock Networks, Inc., Richardson, TX 04/00 – 04/02

Principle System/Hardware Engineer

System Engineering responsibilities include system architectures and requirements

Developed requirements for a 10-Gbps SONET/SDH Framer ASIC capable of supporting 16x OC-3/12 (155/622 Mbps) port configurable, 4x OC-48 (2.488 Gbps), or 1x OC-192 (9.953 Gbps). ASIC can be used in any of the Add/Drop Multiplex (ADM) applications such as Linear Mux, Terminal Mux, UPSR, 2FBLSR, or 4FBLSR.

Part of system engineering group to construct architecture and requirements for release 2 products of a 2-RU OC-192 ADM (linear, terminal, UPSR, BLSR) with OC-3/12/48/192, DS3/EC-1, Gigabit Ethernet, 4/8/32 CWDM, and 100G spacing ITU grid add/drop interfaces.

Performed technology feasibility analysis, created architecture, business case, and product specification, and developed system requirements for a 3-RU (5.25”) DS3/EC-1/DS1 Transport system capable of delivering an aggregated bandwidth of (1+1) 2.488 Gbps (OC-48 equivalent) made up of combination of 48 DS3/EC-1 ports and 84 DS1 ports.

Hardware technical lead of 12 hardware engineers and 3 technicians developing 1st release products: responsibilities include writing white paper and product specification, resource management, project scheduling, design implementation, hardware delivery, software support and coordination, and system testing.

3-RU (5.25”), 48-port DS3/EC1 per port configurable tributary subsystem, (1:n) equipment protection.

Protection scheme (Patent) does not require a unique protection card or active components on backplane.

Architecture is expandable to 96 DS3 interfaces in the same 3-RU footprint.

1-RU (1.75”), SONET ADM (Terminal Mux, Linear Mux, UPSR, 2FBLSR) with interfaces of dual/single OC-48, dual/quad OC-12, quad OC-3, 4/8 CDWDM. The system can be used as either trunk (ring) or tributary node.

Main hardware components used: Optical/Electrical Mux-Dmx/Transceiver/Transponder, Serializer/Deserializer (SerDes), SONET/SDH termination/framer/pointer-processor, STS-1 TSI (Time Slot Interchange), 40G/160G STS-1 XC (cross connect)-TSI (Time Slot Interchange), 10/100 and GBe mapping (GFP/VC), DS3/SONET termination/mapping, Xilinx FPGAs (Spartan, 4000E, Vixtex, Virtex II), Xilinx CPLDs (95XL), Motorola PowerPC MPC8260, Intel Network Processor IXP1200, 128MB/256MB Toshiba SSRAM, 16MB/32MB Intel flash, Stratum 3/3E PLL (Phase Lock Loop) synchronization unit, 2.488Gbps intra-shelf interconnect, and -48V power converter.

Fujitsu Network Communications, Inc., Richardson, TX 08/99 – 04/00

Senior System Engineer

Member of system design team for Add Drop cross connect (ADX) system containing interfaces of DS1, DS3, OC-3/12/48 and EC1 along with switching fabric at STS1, VT1.5 and ATM. New features included dual-OC3, OC-3c/12c Bundling, Transmux, OC48 BLSR, (1:1) Virtual Path Group protection and 10/100 and GBe Ethernet LAN. Responsibilities included product design architecture, product requirement and Network Management Interface definition consisting of TL1 and SNMP.

Alcatel USA, Inc., Plano, TX 07/97 – 07/99

Senior Hardware/System Engineer

Hardware technical lead for OC-48/192 Optical Layer Cross Connect (OLX) subsystem for optical products including protection modules handling 16 OC-48 ports upgradeable to 4 OC-192 ports. Modules consist of 2.4Gbps analog cross point switch, 2.4G O/E & E/O converters, 2.4G CDR, several ASICs and FPGAs performing OC-48 processing.

Member of Hardware design team for ATM subsystem for ATM products including ATM DS3, ATM AAL1 DS1 Circuit Emulation and 520 Mbps Optical interface modules containing multiple ASICs, FPGAs (XC4013XL-HBGA256 and XC4036XL-HBGA352) and sixteen 520-Mbps optical interfaces.

Performed ASIC emulation of Alcatel’s proprietary AAL1 DS1 Circuit Emulation using FPGA solution (XC4085XL-HBGA559).

Main hardware components used: Optical/Electrical Mux-Dmx/Transceiver, Serializer/Deserializer (SerDes), SONET/SDH framer/pointer-processor, SONET/ATM Mapper (OC-3/12), ATM switch (20G). ATM traffic management, Xilinx FPGAs (Spartan, 4000E, Vixtex, Virtex II), Xilinx CPLDs (95XL), Motorola PowerPC MPC8260, SSRAM, flash PLL (Phase Lock Loop) synchronization unit, 622Mbps multi-channel (8) parallel optics, 622Mbps intra-shelf interconnect, and -48V power converter. Optical interface modules containing multiple ASICs, FPGAs (XC4013XL-HBGA256 and XC4036XL-HBGA352) and sixteen 520-Mbps optical interfaces.

Interphase Corporation, Dallas, TX 02/96 – 07/97

Senior Hardware Engineer

Member of design team of 4 for next generation ATM SAR ASIC with 64-bit PCI at 33 MHz, ATM traffic of UBR, CBR or ABR and up to 4K Virtual Connections.

Project lead engineer of 2 ATM adapters at 155 Mbps & 25.6 Mbps with PCI and CPCI form factor

Adapters perform OC-3 Segmentation and Reassembly and 25.6 Mbps physical layer functions.

Population options provided for fiber 155 Mbps, UTP5 155 Mbps or UTP3 25.6 Mbps interface.

PCI bus interface is 32-bit at 33 MHz.

Performed emulation process on QuickTurn Realizer emulation system for a ~180K 0.35 m NEC 155Mbps ATM SAR ASIC.

Project lead engineer of 2 Fiber Channel adapters to provide full speed (1.062 Gbps) Fiber Channel with PMC and CPCI form factor. PCI bus interface is 32-bit at 33 MHz.

Member of design team of 2 for an 80K ASIC providing bus connection from 32-bit PCI at 33 MHz to HP FC500 ASIC (TACHYON) for full or quarter speed (1062/266 Mbps)

ASIC resides on 2 Fiber Channel adapters.

Responsibilities include system simulation, functional simulation, pre and post layout verifications and test vector generation.

DSC Communication Corporation, Plano, TX 08/93 – 02/96

Hardware Design Engineer

General Electric / Martin Marietta, Syracuse, NY 05/89 – 07/93

Hardware Design Engineer


MBA, International Marketing Management, University of Dallas, Irving, TX, 05/97 – 08/03; GPA: 3.85

MSEE, Digital Communication & DSP, Syracuse University, Syracuse, NY, 09/91 – 05/93; GPA: 3.38

BSEE, Computer Engineering, Hofstra University, Hempstead, NY, 09/84 – 05/89; GPA: 3.53


US Citizen.


Available upon request.

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